usrp-users@lists.ettus.com
Discussion and technical support related to USRP, UHD, RFNoC
View all threadsHow can I define a global reg variable in Verilog between RFNOC blocks?
How can I define a global reg variable in Verilog between RFNOC blocks?
I developed two RFNOC blocks: RFNOC block A, and RFNOC block B
How can define a reg variable that shares between RFNOC blocks in USRP?
Can anyone guide me?
I study about global reg variable in the Verilog module, see below
link, but I can not do it for RFNOC blocks...
How can implement this mechanism in RFNOC blocks
https://www.edaboard.com/threads/how-to-define-global-variable-in-verilog.174172/
Thanks in advance
For experimental purpose I did something like you say.
Referring to usrp X300
-
add the reg variable to rfnoc_ce_default_inst_x300.v (or the relevant
file for your radio) -
add to the noc _block module declaration an additional input port e.g.
module noc_test #(
parameter NOC_ID = 64'h1234_0000_0000_1234,
parameter STR_SINK_FIFOSIZE = 11,
parameter NUM_PORTS = 1)
(
input bus_clk, input bus_rst,
input ce_clk, input ce_rst,
input [63:0] my_new_port, <---- EXAMPLE, this is my new port
input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
output [63:0] debug
);
- inside rfnoc_ce_default_inst_x300.v (or the relevant file for your
radio) connect the reg variable with the
new port on the noc_block
- Now you can manage the (shared) reg variable from inside the noc block.
Hope this can be of some help.
Have a good day,
paolo
On 7/31/22 17:52, sp wrote:
How can I define a global reg variable in Verilog between RFNOC blocks?
I developed two RFNOC blocks: RFNOC block A, and RFNOC block B
How can define a reg variable that shares between RFNOC blocks in USRP?
Can anyone guide me?
I study about global reg variable in the Verilog module, see below
link, but I can not do it for RFNOC blocks...
How can implement this mechanism in RFNOC blocks
https://www.edaboard.com/threads/how-to-define-global-variable-in-verilog.174172/
Thanks in advance
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
Hi, I tested your way but I have challenges with it. I described it in
the below link. do you have any offer?
Thanks very much
https://lists.ettus.com/empathy/thread/A65LFSBUISOLPBGIRJWSJYBESRPMPEPC
On Mon, Aug 1, 2022 at 1:47 PM Paolo Palana p.palana@itsystems.it wrote:
For experimental purpose I did something like you say.
Referring to usrp X300
-
add the reg variable to rfnoc_ce_default_inst_x300.v (or the relevant
file for your radio) -
add to the noc _block module declaration an additional input port e.g.
module noc_test #(
parameter NOC_ID = 64'h1234_0000_0000_1234,
parameter STR_SINK_FIFOSIZE = 11,
parameter NUM_PORTS = 1)
(
input bus_clk, input bus_rst,
input ce_clk, input ce_rst,
input [63:0] my_new_port, <---- EXAMPLE, this is my new port
input [63:0] i_tdata, input i_tlast, input i_tvalid, output i_tready,
output [63:0] o_tdata, output o_tlast, output o_tvalid, input o_tready,
output [63:0] debug
);
- inside rfnoc_ce_default_inst_x300.v (or the relevant file for your
radio) connect the reg variable with the
new port on the noc_block
- Now you can manage the (shared) reg variable from inside the noc block.
Hope this can be of some help.
Have a good day,
paolo
On 7/31/22 17:52, sp wrote:
How can I define a global reg variable in Verilog between RFNOC blocks?
I developed two RFNOC blocks: RFNOC block A, and RFNOC block B
How can define a reg variable that shares between RFNOC blocks in USRP?
Can anyone guide me?
I study about global reg variable in the Verilog module, see below
link, but I can not do it for RFNOC blocks...
How can implement this mechanism in RFNOC blocks
Thanks in advance
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
Hi sp,
That sounds like a bad idea. How are you planning to synchronize access to that register?
Generally, in almost any context, avoid global state. That makes things complicated and
error prone; this is true for python as much as it is for C++, as much as it is for
digital hardware design (in verilog or any other way); it's even true for design of
mechanical machine factory floors (if you make each processing step as independent from
the other as possible, you increase reliability).
So, I'd recommend you find a different way to exchange information between two blocks.
Exchanging information is the point of RFNoC, by the way.
Best regards,
Marcus
On 31.07.22 17:52, sp wrote:
How can I define a global reg variable in Verilog between RFNOC blocks?
I developed two RFNOC blocks: RFNOC block A, and RFNOC block B
How can define a reg variable that shares between RFNOC blocks in USRP?
Can anyone guide me?
I study about global reg variable in the Verilog module, see below link, but I can not
do it for RFNOC blocks...
How can implement this mechanism in RFNOC blocks
https://www.edaboard.com/threads/how-to-define-global-variable-in-verilog.174172/
Thanks in advance
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
Thanks very much, Marcus. Can explain more? I had not any idea how develop
your way?
On Mon, Nov 7, 2022 at 11:29 PM Marcus Müller marcus.mueller@ettus.com
wrote:
Hi sp,
That sounds like a bad idea. How are you planning to synchronize access to
that register?
Generally, in almost any context, avoid global state. That makes things
complicated and
error prone; this is true for python as much as it is for C++, as much as
it is for
digital hardware design (in verilog or any other way); it's even true for
design of
mechanical machine factory floors (if you make each processing step as
independent from
the other as possible, you increase reliability).
So, I'd recommend you find a different way to exchange information between
two blocks.
Exchanging information is the point of RFNoC, by the way.
Best regards,
Marcus
On 31.07.22 17:52, sp wrote:
How can I define a global reg variable in Verilog between RFNOC blocks?
I developed two RFNOC blocks: RFNOC block A, and RFNOC block B
How can define a reg variable that shares between RFNOC blocks in USRP?
Can anyone guide me?
I study about global reg variable in the Verilog module, see below
link, but I can not
do it for RFNOC blocks...
How can implement this mechanism in RFNOC blocks
Thanks in advance
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
On Mon, Nov 7, 2022 at 6:29 PM Marcus Müller marcus.mueller@ettus.com
wrote:
Hi sp,
That sounds like a bad idea. How are you planning to synchronize access to
that register?
Generally, in almost any context, avoid global state. That makes things
complicated and
error prone; this is true for python as much as it is for C++, as much as
it is for
digital hardware design (in verilog or any other way); it's even true for
design of
mechanical machine factory floors (if you make each processing step as
independent from
the other as possible, you increase reliability).
As a point of order, though, reducing redundancy is also an admirable goal.
I think the idea of sharing registers between multiple RFNoC blocks is not
a bad idea. It's the idea of a single configuration space with fanouts to
multiple consumers. In C++, imagine it as a singleton of configuration
parameters to be referenced during execution.
As a practical example, imagine you have a TDMA system which needs timings
defined by which the TX and RX both adhere. Or a modulation/coding scheme
which is shared between RX and TX. These are independent blocks with
common configuration items. A suggestion to duplicate registers would not
be seen as appropriate - there is a singular configuration space with
fanout to multiple blocks.
From an FPGA perspective, it is not unheard of that a registerfile may be
common amongst numerous individual blocks which make up a system. The
suggestion earlier, I believe, was to have a custom input to the block
which is the shared configuration space.
Now, speaking in terms of RFNoC, I imagine this as an RFNoC block which is
the configuration space, and has no flows in or out but only exists in the
register space. It has outputs which fanout but no other inputs.
Is there a document which describes how to build this type of system with
RFNoC? Custom output/input port automatically instantiated with the
system? Or does it need to be a custom instantiation after the rest of it
has been templated?
Thanks,
Brian
Thanks, Brain, I emphasize my problem is like your description.
I have a TX and RX with USRP. I used a gain block
for TX and a multiply block for RX.
When In Receiver or RX multiply result is more than a threshold...I want to
change the gain block in TX or Transmitter...
See the screenshot below, I need two blocks to be separately ........
[image: image.png]
On Tue, Nov 8, 2022 at 6:39 PM Brian Padalino bpadalino@gmail.com wrote:
On Mon, Nov 7, 2022 at 6:29 PM Marcus Müller marcus.mueller@ettus.com
wrote:
Hi sp,
That sounds like a bad idea. How are you planning to synchronize access
to that register?
Generally, in almost any context, avoid global state. That makes things
complicated and
error prone; this is true for python as much as it is for C++, as much as
it is for
digital hardware design (in verilog or any other way); it's even true for
design of
mechanical machine factory floors (if you make each processing step as
independent from
the other as possible, you increase reliability).
As a point of order, though, reducing redundancy is also an admirable goal.
I think the idea of sharing registers between multiple RFNoC blocks is not
a bad idea. It's the idea of a single configuration space with fanouts to
multiple consumers. In C++, imagine it as a singleton of configuration
parameters to be referenced during execution.
As a practical example, imagine you have a TDMA system which needs timings
defined by which the TX and RX both adhere. Or a modulation/coding scheme
which is shared between RX and TX. These are independent blocks with
common configuration items. A suggestion to duplicate registers would not
be seen as appropriate - there is a singular configuration space with
fanout to multiple blocks.
From an FPGA perspective, it is not unheard of that a registerfile may be
common amongst numerous individual blocks which make up a system. The
suggestion earlier, I believe, was to have a custom input to the block
which is the shared configuration space.
Now, speaking in terms of RFNoC, I imagine this as an RFNoC block which is
the configuration space, and has no flows in or out but only exists in the
register space. It has outputs which fanout but no other inputs.
Is there a document which describes how to build this type of system with
RFNoC? Custom output/input port automatically instantiated with the
system? Or does it need to be a custom instantiation after the rest of it
has been templated?
Thanks,
Brian
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
Finally, I developed a reg shared between blocks. it works. Everything is
ok.
I used a guide from Paolo Palana. You can see in the below link. Thanks
very much
On Tue, Nov 8, 2022 at 7:20 PM sp stackprogramer@gmail.com wrote:
Thanks, Brain, I emphasize my problem is like your description.
I have a TX and RX with USRP. I used a gain block
for TX and a multiply block for RX.
When In Receiver or RX multiply result is more than a threshold...I want to
change the gain block in TX or Transmitter...
See the screenshot below, I need two blocks to be separately ........
[image: image.png]
On Tue, Nov 8, 2022 at 6:39 PM Brian Padalino bpadalino@gmail.com wrote:
On Mon, Nov 7, 2022 at 6:29 PM Marcus Müller marcus.mueller@ettus.com
wrote:
Hi sp,
That sounds like a bad idea. How are you planning to synchronize access
to that register?
Generally, in almost any context, avoid global state. That makes
things complicated and
error prone; this is true for python as much as it is for C++, as much
as it is for
digital hardware design (in verilog or any other way); it's even true
for design of
mechanical machine factory floors (if you make each processing step as
independent from
the other as possible, you increase reliability).
As a point of order, though, reducing redundancy is also an admirable
goal.
I think the idea of sharing registers between multiple RFNoC blocks is
not a bad idea. It's the idea of a single configuration space with fanouts
to multiple consumers. In C++, imagine it as a singleton of configuration
parameters to be referenced during execution.
As a practical example, imagine you have a TDMA system which needs
timings defined by which the TX and RX both adhere. Or a modulation/coding
scheme which is shared between RX and TX. These are independent blocks
with common configuration items. A suggestion to duplicate registers would
not be seen as appropriate - there is a singular configuration space with
fanout to multiple blocks.
From an FPGA perspective, it is not unheard of that a registerfile may be
common amongst numerous individual blocks which make up a system. The
suggestion earlier, I believe, was to have a custom input to the block
which is the shared configuration space.
Now, speaking in terms of RFNoC, I imagine this as an RFNoC block which
is the configuration space, and has no flows in or out but only exists in
the register space. It has outputs which fanout but no other inputs.
Is there a document which describes how to build this type of system with
RFNoC? Custom output/input port automatically instantiated with the
system? Or does it need to be a custom instantiation after the rest of it
has been templated?
Thanks,
Brian
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
