List: usrp-users@lists.ettus.com
From: BHUSHAN PAWAR
Re: [USRP-users] E310 : Interfacing ZynQ 7020 with AD 9361 RFIC and Filter Banks
Mon, Feb 15, 2016 3:08 PM
Hi all,
I am using the source code from Github usrp3/top/e300 and trying to
synthesize the code. However, I am getting these errors. Kindly help.
[image: Inline image 2][image: Inline image 1]
*Thanks !!*
On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas wrote:
> Hi Pawar,
>
> The FPGA sources are to modify the FPGA.