Hi Pawar, The FPGA sources are to modify the FPGA. The FPGA is larger than the image it currently holds. Many people use it to add aditional filters, FFTs, etc. Adding on top of what already exists and is needed for correct functionality...But you need to know Vivado for that. Check also RFNOC, it may be easier:) PS: Plz keep discussion in group, so that others may benefit as well... HTH, Nikos On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR <bhushan.rv.pawar@gmail.com> wrote: > Hi Nikos, > > Thanks for the reply. > > Then can you explain me what is the real use of the FPGA code on > usrp3/top/e300 subdirectory on github. > > How can I use this code to get started? > > > > *Thanks & Regards,* > > *Bhushan R.V. Pawar.* > > > On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <nbalkanas@gmail.com> > wrote: > >> Hi, >> >> Have you also tried vivado forums? They can help more than what we can >> here... >> Plz post your errors. Recently started on vivado myself, and the only >> errors I got were from licensing issues for my FPGA. >> I have an X300 >> >> HTH, >> Nikos >> >> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> Dear Moritz, >>> >>> Thank you for the reply. >>> >>> I want to use E310 as multi channel transmitter and receiver and want to >>> test it using signal generator and oscilloscope. >>> >>> I tried to import the code from usrp3/top/e300 subdirectory into Vivado >>> 2015.4 but it is giving many errors when I try to synthesize it. >>> >>> Can you explain me step by step, how to work with E310. >>> >>> >>> >>> >>> *Thanks !!* >>> >>> >>> >>> >>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer < >>> moritz.fischer@ettus.com> wrote: >>> >>>> Hi Bhushan, >>>> >>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >>>> <usrp-users@lists.ettus.com> wrote: >>>> > Hello, >>>> > >>>> > I am trying to build multi channel transmitter and receiver using >>>> USRP E310. >>>> >>>> all our code for E310 is open-source. Feel free to peruse our github. >>>> On the FPGA side you might wanna look at the usrp3/top/e300 >>>> subdirectory [1]. >>>> >>>> If you let us know what exactly you're trying to do, people can help >>>> you out easier. >>>> > However I am new to FPGA programming, hence I am facing a lot of >>>> challenges >>>> > in interfacing ZynQ board with the transceiver and filter banks in >>>> Vivado >>>> > 2015.4. >>>> > Is to possible to get few demo projects which might help me to >>>> understand >>>> > the data flow in the simple transmitter and receiver application? >>>> Kindly >>>> > share few useful documents which will help me to understand the above >>>> > problem. >>>> >>>> Again, all our code for E310 is open source (apart from Xilinx IP). >>>> Feel free to dig through the code. >>>> The filter bank settings are documented in the UHD manual [2]. >>>> >>>> Good luck, >>>> >>>> Moritz >>>> >>>> [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >>>> >>> >>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >> >

Hi all, I am using the source code from Github usrp3/top/e300 and trying to synthesize the code. However, I am getting these errors. Kindly help. [image: Inline image 2][image: Inline image 1] *Thanks !!* On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <nbalkanas@gmail.com> wrote: > Hi Pawar, > > The FPGA sources are to modify the FPGA. The FPGA is larger than the image > it currently holds. Many people use it to add aditional filters, FFTs, etc. > Adding on top of what already exists and is needed for correct > functionality...But you need to know Vivado for that. Check also RFNOC, it > may be easier:) > > PS: Plz keep discussion in group, so that others may benefit as well... > > HTH, > Nikos > > On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR <bhushan.rv.pawar@gmail.com > > wrote: > >> Hi Nikos, >> >> Thanks for the reply. >> >> Then can you explain me what is the real use of the FPGA code on >> usrp3/top/e300 subdirectory on github. >> >> How can I use this code to get started? >> >> >> >> *Thanks & Regards,* >> >> *Bhushan R.V. Pawar.* >> >> >> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <nbalkanas@gmail.com> >> wrote: >> >>> Hi, >>> >>> Have you also tried vivado forums? They can help more than what we can >>> here... >>> Plz post your errors. Recently started on vivado myself, and the only >>> errors I got were from licensing issues for my FPGA. >>> I have an X300 >>> >>> HTH, >>> Nikos >>> >>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < >>> usrp-users@lists.ettus.com> wrote: >>> >>>> Dear Moritz, >>>> >>>> Thank you for the reply. >>>> >>>> I want to use E310 as multi channel transmitter and receiver and want >>>> to test it using signal generator and oscilloscope. >>>> >>>> I tried to import the code from usrp3/top/e300 subdirectory into >>>> Vivado 2015.4 but it is giving many errors when I try to synthesize it. >>>> >>>> Can you explain me step by step, how to work with E310. >>>> >>>> >>>> >>>> >>>> *Thanks !!* >>>> >>>> >>>> >>>> >>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer < >>>> moritz.fischer@ettus.com> wrote: >>>> >>>>> Hi Bhushan, >>>>> >>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >>>>> <usrp-users@lists.ettus.com> wrote: >>>>> > Hello, >>>>> > >>>>> > I am trying to build multi channel transmitter and receiver using >>>>> USRP E310. >>>>> >>>>> all our code for E310 is open-source. Feel free to peruse our github. >>>>> On the FPGA side you might wanna look at the usrp3/top/e300 >>>>> subdirectory [1]. >>>>> >>>>> If you let us know what exactly you're trying to do, people can help >>>>> you out easier. >>>>> > However I am new to FPGA programming, hence I am facing a lot of >>>>> challenges >>>>> > in interfacing ZynQ board with the transceiver and filter banks in >>>>> Vivado >>>>> > 2015.4. >>>>> > Is to possible to get few demo projects which might help me to >>>>> understand >>>>> > the data flow in the simple transmitter and receiver application? >>>>> Kindly >>>>> > share few useful documents which will help me to understand the above >>>>> > problem. >>>>> >>>>> Again, all our code for E310 is open source (apart from Xilinx IP). >>>>> Feel free to dig through the code. >>>>> The filter bank settings are documented in the UHD manual [2]. >>>>> >>>>> Good luck, >>>>> >>>>> Moritz >>>>> >>>>> [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >>>>> >>>> >>>> >>>> _______________________________________________ >>>> USRP-users mailing list >>>> USRP-users@lists.ettus.com >>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>> >>>> >>> >> >

Sorry, I can't read those, too small :(. Plz post your errors. Nikos On Mon, Feb 15, 2016 at 5:08 PM, BHUSHAN PAWAR <bhushan.rv.pawar@gmail.com> wrote: > Hi all, > > I am using the source code from Github usrp3/top/e300 and trying to > synthesize the code. However, I am getting these errors. Kindly help. > > [image: Inline image 2][image: Inline image 1] > > > *Thanks !!* > > > On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <nbalkanas@gmail.com> > wrote: > >> Hi Pawar, >> >> The FPGA sources are to modify the FPGA. The FPGA is larger than the >> image it currently holds. Many people use it to add aditional filters, >> FFTs, etc. >> Adding on top of what already exists and is needed for correct >> functionality...But you need to know Vivado for that. Check also RFNOC, it >> may be easier:) >> >> PS: Plz keep discussion in group, so that others may benefit as well... >> >> HTH, >> Nikos >> >> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR < >> bhushan.rv.pawar@gmail.com> wrote: >> >>> Hi Nikos, >>> >>> Thanks for the reply. >>> >>> Then can you explain me what is the real use of the FPGA code on >>> usrp3/top/e300 subdirectory on github. >>> >>> How can I use this code to get started? >>> >>> >>> >>> *Thanks & Regards,* >>> >>> *Bhushan R.V. Pawar.* >>> >>> >>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <nbalkanas@gmail.com> >>> wrote: >>> >>>> Hi, >>>> >>>> Have you also tried vivado forums? They can help more than what we can >>>> here... >>>> Plz post your errors. Recently started on vivado myself, and the only >>>> errors I got were from licensing issues for my FPGA. >>>> I have an X300 >>>> >>>> HTH, >>>> Nikos >>>> >>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < >>>> usrp-users@lists.ettus.com> wrote: >>>> >>>>> Dear Moritz, >>>>> >>>>> Thank you for the reply. >>>>> >>>>> I want to use E310 as multi channel transmitter and receiver and want >>>>> to test it using signal generator and oscilloscope. >>>>> >>>>> I tried to import the code from usrp3/top/e300 subdirectory into >>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize it. >>>>> >>>>> Can you explain me step by step, how to work with E310. >>>>> >>>>> >>>>> >>>>> >>>>> *Thanks !!* >>>>> >>>>> >>>>> >>>>> >>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer < >>>>> moritz.fischer@ettus.com> wrote: >>>>> >>>>>> Hi Bhushan, >>>>>> >>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >>>>>> <usrp-users@lists.ettus.com> wrote: >>>>>> > Hello, >>>>>> > >>>>>> > I am trying to build multi channel transmitter and receiver using >>>>>> USRP E310. >>>>>> >>>>>> all our code for E310 is open-source. Feel free to peruse our github. >>>>>> On the FPGA side you might wanna look at the usrp3/top/e300 >>>>>> subdirectory [1]. >>>>>> >>>>>> If you let us know what exactly you're trying to do, people can help >>>>>> you out easier. >>>>>> > However I am new to FPGA programming, hence I am facing a lot of >>>>>> challenges >>>>>> > in interfacing ZynQ board with the transceiver and filter banks in >>>>>> Vivado >>>>>> > 2015.4. >>>>>> > Is to possible to get few demo projects which might help me to >>>>>> understand >>>>>> > the data flow in the simple transmitter and receiver application? >>>>>> Kindly >>>>>> > share few useful documents which will help me to understand the >>>>>> above >>>>>> > problem. >>>>>> >>>>>> Again, all our code for E310 is open source (apart from Xilinx IP). >>>>>> Feel free to dig through the code. >>>>>> The filter bank settings are documented in the UHD manual [2]. >>>>>> >>>>>> Good luck, >>>>>> >>>>>> Moritz >>>>>> >>>>>> [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >>>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> USRP-users mailing list >>>>> USRP-users@lists.ettus.com >>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>>> >>>>> >>>> >>> >> >

Hi, You will need to follow the instructions for building the FPGA image here: http://files.ettus.com/manual/md_usrp3_build_instructions.html There is a makefile target for the E310 that will build the FPGA image. -Trip On Mon, Feb 15, 2016 at 10:08 AM, BHUSHAN PAWAR via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi all, > > I am using the source code from Github usrp3/top/e300 and trying to > synthesize the code. However, I am getting these errors. Kindly help. > > [image: Inline image 2][image: Inline image 1] > > > *Thanks !!* > > > On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <nbalkanas@gmail.com> > wrote: > >> Hi Pawar, >> >> The FPGA sources are to modify the FPGA. The FPGA is larger than the >> image it currently holds. Many people use it to add aditional filters, >> FFTs, etc. >> Adding on top of what already exists and is needed for correct >> functionality...But you need to know Vivado for that. Check also RFNOC, it >> may be easier:) >> >> PS: Plz keep discussion in group, so that others may benefit as well... >> >> HTH, >> Nikos >> >> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR < >> bhushan.rv.pawar@gmail.com> wrote: >> >>> Hi Nikos, >>> >>> Thanks for the reply. >>> >>> Then can you explain me what is the real use of the FPGA code on >>> usrp3/top/e300 subdirectory on github. >>> >>> How can I use this code to get started? >>> >>> >>> >>> *Thanks & Regards,* >>> >>> *Bhushan R.V. Pawar.* >>> >>> >>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <nbalkanas@gmail.com> >>> wrote: >>> >>>> Hi, >>>> >>>> Have you also tried vivado forums? They can help more than what we can >>>> here... >>>> Plz post your errors. Recently started on vivado myself, and the only >>>> errors I got were from licensing issues for my FPGA. >>>> I have an X300 >>>> >>>> HTH, >>>> Nikos >>>> >>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < >>>> usrp-users@lists.ettus.com> wrote: >>>> >>>>> Dear Moritz, >>>>> >>>>> Thank you for the reply. >>>>> >>>>> I want to use E310 as multi channel transmitter and receiver and want >>>>> to test it using signal generator and oscilloscope. >>>>> >>>>> I tried to import the code from usrp3/top/e300 subdirectory into >>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize it. >>>>> >>>>> Can you explain me step by step, how to work with E310. >>>>> >>>>> >>>>> >>>>> >>>>> *Thanks !!* >>>>> >>>>> >>>>> >>>>> >>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer < >>>>> moritz.fischer@ettus.com> wrote: >>>>> >>>>>> Hi Bhushan, >>>>>> >>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >>>>>> <usrp-users@lists.ettus.com> wrote: >>>>>> > Hello, >>>>>> > >>>>>> > I am trying to build multi channel transmitter and receiver using >>>>>> USRP E310. >>>>>> >>>>>> all our code for E310 is open-source. Feel free to peruse our github. >>>>>> On the FPGA side you might wanna look at the usrp3/top/e300 >>>>>> subdirectory [1]. >>>>>> >>>>>> If you let us know what exactly you're trying to do, people can help >>>>>> you out easier. >>>>>> > However I am new to FPGA programming, hence I am facing a lot of >>>>>> challenges >>>>>> > in interfacing ZynQ board with the transceiver and filter banks in >>>>>> Vivado >>>>>> > 2015.4. >>>>>> > Is to possible to get few demo projects which might help me to >>>>>> understand >>>>>> > the data flow in the simple transmitter and receiver application? >>>>>> Kindly >>>>>> > share few useful documents which will help me to understand the >>>>>> above >>>>>> > problem. >>>>>> >>>>>> Again, all our code for E310 is open source (apart from Xilinx IP). >>>>>> Feel free to dig through the code. >>>>>> The filter bank settings are documented in the UHD manual [2]. >>>>>> >>>>>> Good luck, >>>>>> >>>>>> Moritz >>>>>> >>>>>> [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >>>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> USRP-users mailing list >>>>> USRP-users@lists.ettus.com >>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>>> >>>>> >>>> >>> >> > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

Errors: [Synthv8-448] named port connection 'GPIO_I' does not exist for instance 'inst_processing_system7' of module 'processing_system7_1' [e3xx_ps.v.263] (85 more like this) [Synthv8-285] failed synthesizing module 'axi4_fifo_512x64' [axi4_fifo_512x64_stub.v.7] (2 more like this) *Thanks & Regards,* *Bhushan R.V. Pawar.* *(+49-17685263152)* On Mon, Feb 15, 2016 at 4:08 PM, BHUSHAN PAWAR <bhushan.rv.pawar@gmail.com> wrote: > Hi all, > > I am using the source code from Github usrp3/top/e300 and trying to > synthesize the code. However, I am getting these errors. Kindly help. > > [image: Inline image 2][image: Inline image 1] > > > *Thanks !!* > > > On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <nbalkanas@gmail.com> > wrote: > >> Hi Pawar, >> >> The FPGA sources are to modify the FPGA. The FPGA is larger than the >> image it currently holds. Many people use it to add aditional filters, >> FFTs, etc. >> Adding on top of what already exists and is needed for correct >> functionality...But you need to know Vivado for that. Check also RFNOC, it >> may be easier:) >> >> PS: Plz keep discussion in group, so that others may benefit as well... >> >> HTH, >> Nikos >> >> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR < >> bhushan.rv.pawar@gmail.com> wrote: >> >>> Hi Nikos, >>> >>> Thanks for the reply. >>> >>> Then can you explain me what is the real use of the FPGA code on >>> usrp3/top/e300 subdirectory on github. >>> >>> How can I use this code to get started? >>> >>> >>> >>> *Thanks & Regards,* >>> >>> *Bhushan R.V. Pawar.* >>> >>> >>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <nbalkanas@gmail.com> >>> wrote: >>> >>>> Hi, >>>> >>>> Have you also tried vivado forums? They can help more than what we can >>>> here... >>>> Plz post your errors. Recently started on vivado myself, and the only >>>> errors I got were from licensing issues for my FPGA. >>>> I have an X300 >>>> >>>> HTH, >>>> Nikos >>>> >>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < >>>> usrp-users@lists.ettus.com> wrote: >>>> >>>>> Dear Moritz, >>>>> >>>>> Thank you for the reply. >>>>> >>>>> I want to use E310 as multi channel transmitter and receiver and want >>>>> to test it using signal generator and oscilloscope. >>>>> >>>>> I tried to import the code from usrp3/top/e300 subdirectory into >>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize it. >>>>> >>>>> Can you explain me step by step, how to work with E310. >>>>> >>>>> >>>>> >>>>> >>>>> *Thanks !!* >>>>> >>>>> >>>>> >>>>> >>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer < >>>>> moritz.fischer@ettus.com> wrote: >>>>> >>>>>> Hi Bhushan, >>>>>> >>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >>>>>> <usrp-users@lists.ettus.com> wrote: >>>>>> > Hello, >>>>>> > >>>>>> > I am trying to build multi channel transmitter and receiver using >>>>>> USRP E310. >>>>>> >>>>>> all our code for E310 is open-source. Feel free to peruse our github. >>>>>> On the FPGA side you might wanna look at the usrp3/top/e300 >>>>>> subdirectory [1]. >>>>>> >>>>>> If you let us know what exactly you're trying to do, people can help >>>>>> you out easier. >>>>>> > However I am new to FPGA programming, hence I am facing a lot of >>>>>> challenges >>>>>> > in interfacing ZynQ board with the transceiver and filter banks in >>>>>> Vivado >>>>>> > 2015.4. >>>>>> > Is to possible to get few demo projects which might help me to >>>>>> understand >>>>>> > the data flow in the simple transmitter and receiver application? >>>>>> Kindly >>>>>> > share few useful documents which will help me to understand the >>>>>> above >>>>>> > problem. >>>>>> >>>>>> Again, all our code for E310 is open source (apart from Xilinx IP). >>>>>> Feel free to dig through the code. >>>>>> The filter bank settings are documented in the UHD manual [2]. >>>>>> >>>>>> Good luck, >>>>>> >>>>>> Moritz >>>>>> >>>>>> [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >>>>>> >>>>> >>>>> >>>>> _______________________________________________ >>>>> USRP-users mailing list >>>>> USRP-users@lists.ettus.com >>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>>> >>>>> >>>> >>> >> >

Hi, Did you followed the Makefile procedure indicated by James? What target did you build? Nikos On Mon, Feb 15, 2016 at 5:26 PM, BHUSHAN PAWAR <bhushan.rv.pawar@gmail.com> wrote: > Errors: > > [Synthv8-448] named port connection 'GPIO_I' does not exist for instance > 'inst_processing_system7' of module 'processing_system7_1' [e3xx_ps.v.263] > (85 more like this) > > [Synthv8-285] failed synthesizing module 'axi4_fifo_512x64' > [axi4_fifo_512x64_stub.v.7] > (2 more like this) > > *Thanks & Regards,* > > *Bhushan R.V. Pawar.* > *(+49-17685263152 <%28%2B49-17685263152>)* > > > On Mon, Feb 15, 2016 at 4:08 PM, BHUSHAN PAWAR <bhushan.rv.pawar@gmail.com > > wrote: > >> Hi all, >> >> I am using the source code from Github usrp3/top/e300 and trying to >> synthesize the code. However, I am getting these errors. Kindly help. >> >> [image: Inline image 2][image: Inline image 1] >> >> >> *Thanks !!* >> >> >> On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <nbalkanas@gmail.com> >> wrote: >> >>> Hi Pawar, >>> >>> The FPGA sources are to modify the FPGA. The FPGA is larger than the >>> image it currently holds. Many people use it to add aditional filters, >>> FFTs, etc. >>> Adding on top of what already exists and is needed for correct >>> functionality...But you need to know Vivado for that. Check also RFNOC, it >>> may be easier:) >>> >>> PS: Plz keep discussion in group, so that others may benefit as well... >>> >>> HTH, >>> Nikos >>> >>> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR < >>> bhushan.rv.pawar@gmail.com> wrote: >>> >>>> Hi Nikos, >>>> >>>> Thanks for the reply. >>>> >>>> Then can you explain me what is the real use of the FPGA code on >>>> usrp3/top/e300 subdirectory on github. >>>> >>>> How can I use this code to get started? >>>> >>>> >>>> >>>> *Thanks & Regards,* >>>> >>>> *Bhushan R.V. Pawar.* >>>> >>>> >>>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <nbalkanas@gmail.com> >>>> wrote: >>>> >>>>> Hi, >>>>> >>>>> Have you also tried vivado forums? They can help more than what we can >>>>> here... >>>>> Plz post your errors. Recently started on vivado myself, and the only >>>>> errors I got were from licensing issues for my FPGA. >>>>> I have an X300 >>>>> >>>>> HTH, >>>>> Nikos >>>>> >>>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < >>>>> usrp-users@lists.ettus.com> wrote: >>>>> >>>>>> Dear Moritz, >>>>>> >>>>>> Thank you for the reply. >>>>>> >>>>>> I want to use E310 as multi channel transmitter and receiver and want >>>>>> to test it using signal generator and oscilloscope. >>>>>> >>>>>> I tried to import the code from usrp3/top/e300 subdirectory into >>>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize it. >>>>>> >>>>>> Can you explain me step by step, how to work with E310. >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> *Thanks !!* >>>>>> >>>>>> >>>>>> >>>>>> >>>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer < >>>>>> moritz.fischer@ettus.com> wrote: >>>>>> >>>>>>> Hi Bhushan, >>>>>>> >>>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >>>>>>> <usrp-users@lists.ettus.com> wrote: >>>>>>> > Hello, >>>>>>> > >>>>>>> > I am trying to build multi channel transmitter and receiver using >>>>>>> USRP E310. >>>>>>> >>>>>>> all our code for E310 is open-source. Feel free to peruse our github. >>>>>>> On the FPGA side you might wanna look at the usrp3/top/e300 >>>>>>> subdirectory [1]. >>>>>>> >>>>>>> If you let us know what exactly you're trying to do, people can help >>>>>>> you out easier. >>>>>>> > However I am new to FPGA programming, hence I am facing a lot of >>>>>>> challenges >>>>>>> > in interfacing ZynQ board with the transceiver and filter banks in >>>>>>> Vivado >>>>>>> > 2015.4. >>>>>>> > Is to possible to get few demo projects which might help me to >>>>>>> understand >>>>>>> > the data flow in the simple transmitter and receiver application? >>>>>>> Kindly >>>>>>> > share few useful documents which will help me to understand the >>>>>>> above >>>>>>> > problem. >>>>>>> >>>>>>> Again, all our code for E310 is open source (apart from Xilinx IP). >>>>>>> Feel free to dig through the code. >>>>>>> The filter bank settings are documented in the UHD manual [2]. >>>>>>> >>>>>>> Good luck, >>>>>>> >>>>>>> Moritz >>>>>>> >>>>>>> [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >>>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >>>>>>> >>>>>> >>>>>> >>>>>> _______________________________________________ >>>>>> USRP-users mailing list >>>>>> USRP-users@lists.ettus.com >>>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>>>> >>>>>> >>>>> >>>> >>> >> >

Hi Pawar, It looks like you created a Vivado project file and then manually imported source files. I would suggest instead running make with GUI=1, i.e. make GUI=1 E310. This will load the Vivado GUI and you can save a project file from there (File->Save Project As...). Jonathon On Mon, Feb 15, 2016 at 8:05 AM, Nikos Balkanas via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > Did you followed the Makefile procedure indicated by James? What target > did you build? > > Nikos > > On Mon, Feb 15, 2016 at 5:26 PM, BHUSHAN PAWAR <bhushan.rv.pawar@gmail.com > > wrote: > >> Errors: >> >> [Synthv8-448] named port connection 'GPIO_I' does not exist for instance >> 'inst_processing_system7' of module 'processing_system7_1' [e3xx_ps.v.263] >> (85 more like this) >> >> [Synthv8-285] failed synthesizing module 'axi4_fifo_512x64' >> [axi4_fifo_512x64_stub.v.7] >> (2 more like this) >> >> *Thanks & Regards,* >> >> *Bhushan R.V. Pawar.* >> *(+49-17685263152 <%28%2B49-17685263152>)* >> >> >> On Mon, Feb 15, 2016 at 4:08 PM, BHUSHAN PAWAR < >> bhushan.rv.pawar@gmail.com> wrote: >> >>> Hi all, >>> >>> I am using the source code from Github usrp3/top/e300 and trying to >>> synthesize the code. However, I am getting these errors. Kindly help. >>> >>> [image: Inline image 2][image: Inline image 1] >>> >>> >>> *Thanks !!* >>> >>> >>> On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <nbalkanas@gmail.com> >>> wrote: >>> >>>> Hi Pawar, >>>> >>>> The FPGA sources are to modify the FPGA. The FPGA is larger than the >>>> image it currently holds. Many people use it to add aditional filters, >>>> FFTs, etc. >>>> Adding on top of what already exists and is needed for correct >>>> functionality...But you need to know Vivado for that. Check also RFNOC, it >>>> may be easier:) >>>> >>>> PS: Plz keep discussion in group, so that others may benefit as well... >>>> >>>> HTH, >>>> Nikos >>>> >>>> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR < >>>> bhushan.rv.pawar@gmail.com> wrote: >>>> >>>>> Hi Nikos, >>>>> >>>>> Thanks for the reply. >>>>> >>>>> Then can you explain me what is the real use of the FPGA code on >>>>> usrp3/top/e300 subdirectory on github. >>>>> >>>>> How can I use this code to get started? >>>>> >>>>> >>>>> >>>>> *Thanks & Regards,* >>>>> >>>>> *Bhushan R.V. Pawar.* >>>>> >>>>> >>>>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <nbalkanas@gmail.com> >>>>> wrote: >>>>> >>>>>> Hi, >>>>>> >>>>>> Have you also tried vivado forums? They can help more than what we >>>>>> can here... >>>>>> Plz post your errors. Recently started on vivado myself, and the only >>>>>> errors I got were from licensing issues for my FPGA. >>>>>> I have an X300 >>>>>> >>>>>> HTH, >>>>>> Nikos >>>>>> >>>>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < >>>>>> usrp-users@lists.ettus.com> wrote: >>>>>> >>>>>>> Dear Moritz, >>>>>>> >>>>>>> Thank you for the reply. >>>>>>> >>>>>>> I want to use E310 as multi channel transmitter and receiver and >>>>>>> want to test it using signal generator and oscilloscope. >>>>>>> >>>>>>> I tried to import the code from usrp3/top/e300 subdirectory into >>>>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize it. >>>>>>> >>>>>>> Can you explain me step by step, how to work with E310. >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>>> *Thanks !!* >>>>>>> >>>>>>> >>>>>>> >>>>>>> >>>>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer < >>>>>>> moritz.fischer@ettus.com> wrote: >>>>>>> >>>>>>>> Hi Bhushan, >>>>>>>> >>>>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >>>>>>>> <usrp-users@lists.ettus.com> wrote: >>>>>>>> > Hello, >>>>>>>> > >>>>>>>> > I am trying to build multi channel transmitter and receiver using >>>>>>>> USRP E310. >>>>>>>> >>>>>>>> all our code for E310 is open-source. Feel free to peruse our >>>>>>>> github. >>>>>>>> On the FPGA side you might wanna look at the usrp3/top/e300 >>>>>>>> subdirectory [1]. >>>>>>>> >>>>>>>> If you let us know what exactly you're trying to do, people can help >>>>>>>> you out easier. >>>>>>>> > However I am new to FPGA programming, hence I am facing a lot of >>>>>>>> challenges >>>>>>>> > in interfacing ZynQ board with the transceiver and filter banks >>>>>>>> in Vivado >>>>>>>> > 2015.4. >>>>>>>> > Is to possible to get few demo projects which might help me to >>>>>>>> understand >>>>>>>> > the data flow in the simple transmitter and receiver application? >>>>>>>> Kindly >>>>>>>> > share few useful documents which will help me to understand the >>>>>>>> above >>>>>>>> > problem. >>>>>>>> >>>>>>>> Again, all our code for E310 is open source (apart from Xilinx IP). >>>>>>>> Feel free to dig through the code. >>>>>>>> The filter bank settings are documented in the UHD manual [2]. >>>>>>>> >>>>>>>> Good luck, >>>>>>>> >>>>>>>> Moritz >>>>>>>> >>>>>>>> [1] >>>>>>>> https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >>>>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >>>>>>>> >>>>>>> >>>>>>> >>>>>>> _______________________________________________ >>>>>>> USRP-users mailing list >>>>>>> USRP-users@lists.ettus.com >>>>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

Dear Jonathon, Thanks for your reply. I followed your suggestion and and to build the project using command 'make E310 GUI=1'. It opened the GUI for Vivado, however before I could save the project there was an error and Vivado was closed automatically. Below are the lines from terminal also I am attaching the log file with this email, [pawa_bh@ohff24 e300]$ chmod u+x setupenv.sh [pawa_bh@ohff24 e300]$ . setupenv.sh Setting up X3x0 FPGA build environment (64-bit)... bash: /opt/Xilinx/Vivado_HLS/Vivado/2014.4/.settings64-Vivado_High_Level_Synthesis.sh: Datei oder Verzeichnis nicht gefunden - Vivado: Found (/opt/Xilinx/Vivado/Vivado/2014.4/bin) Environment successfully initialized. [pawa_bh@ohff24 e300]$ make E310 GUI=1 make -f Makefile.e300.inc bin NAME=E310 ARCH=zynq PART_ID=xc7z020/clg484/-1 EXTRA_DEFS="E310" make[1]: Entering directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300' Vivado v2014.4 (64-bit) ****** Vivado v2014.4 (64-bit) **** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014 **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. start_gui Abnormal program termination (11) Please check '/home/pawa_bh/uhd/fpga-src/usrp3/top/e300/build-E310/hs_err_pid12758.log' for details make[1]: *** [bin] Fehler 139 make[1]: Leaving directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300' make: *** [E310] Fehler 2 [pawa_bh@ohff24 e300]$ I tried building the project with only make E310 command and the bit file was generated without any error. Kindly help me to resolve this issue. *Thanks & Regards,* *Bhushan R.V. Pawar.* On Mon, Feb 15, 2016 at 11:14 PM, Jonathon Pendlum < jonathon.pendlum@ettus.com> wrote: > Hi Pawar, > > It looks like you created a Vivado project file and then manually imported > source files. I would suggest instead running make with GUI=1, i.e. make > GUI=1 E310. This will load the Vivado GUI and you can save a project file > from there (File->Save Project As...). > > > > Jonathon > > On Mon, Feb 15, 2016 at 8:05 AM, Nikos Balkanas via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi, >> >> Did you followed the Makefile procedure indicated by James? What target >> did you build? >> >> Nikos >> >> On Mon, Feb 15, 2016 at 5:26 PM, BHUSHAN PAWAR < >> bhushan.rv.pawar@gmail.com> wrote: >> >>> Errors: >>> >>> [Synthv8-448] named port connection 'GPIO_I' does not exist for instance >>> 'inst_processing_system7' of module 'processing_system7_1' [e3xx_ps.v.263] >>> (85 more like this) >>> >>> [Synthv8-285] failed synthesizing module 'axi4_fifo_512x64' >>> [axi4_fifo_512x64_stub.v.7] >>> (2 more like this) >>> >>> *Thanks & Regards,* >>> >>> *Bhushan R.V. Pawar.* >>> *(+49-17685263152 <%28%2B49-17685263152>)* >>> >>> >>> On Mon, Feb 15, 2016 at 4:08 PM, BHUSHAN PAWAR < >>> bhushan.rv.pawar@gmail.com> wrote: >>> >>>> Hi all, >>>> >>>> I am using the source code from Github usrp3/top/e300 and trying to >>>> synthesize the code. However, I am getting these errors. Kindly help. >>>> >>>> [image: Inline image 2][image: Inline image 1] >>>> >>>> >>>> *Thanks !!* >>>> >>>> >>>> On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <nbalkanas@gmail.com> >>>> wrote: >>>> >>>>> Hi Pawar, >>>>> >>>>> The FPGA sources are to modify the FPGA. The FPGA is larger than the >>>>> image it currently holds. Many people use it to add aditional filters, >>>>> FFTs, etc. >>>>> Adding on top of what already exists and is needed for correct >>>>> functionality...But you need to know Vivado for that. Check also RFNOC, it >>>>> may be easier:) >>>>> >>>>> PS: Plz keep discussion in group, so that others may benefit as well... >>>>> >>>>> HTH, >>>>> Nikos >>>>> >>>>> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR < >>>>> bhushan.rv.pawar@gmail.com> wrote: >>>>> >>>>>> Hi Nikos, >>>>>> >>>>>> Thanks for the reply. >>>>>> >>>>>> Then can you explain me what is the real use of the FPGA code on >>>>>> usrp3/top/e300 subdirectory on github. >>>>>> >>>>>> How can I use this code to get started? >>>>>> >>>>>> >>>>>> >>>>>> *Thanks & Regards,* >>>>>> >>>>>> *Bhushan R.V. Pawar.* >>>>>> >>>>>> >>>>>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas <nbalkanas@gmail.com >>>>>> > wrote: >>>>>> >>>>>>> Hi, >>>>>>> >>>>>>> Have you also tried vivado forums? They can help more than what we >>>>>>> can here... >>>>>>> Plz post your errors. Recently started on vivado myself, and the >>>>>>> only errors I got were from licensing issues for my FPGA. >>>>>>> I have an X300 >>>>>>> >>>>>>> HTH, >>>>>>> Nikos >>>>>>> >>>>>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < >>>>>>> usrp-users@lists.ettus.com> wrote: >>>>>>> >>>>>>>> Dear Moritz, >>>>>>>> >>>>>>>> Thank you for the reply. >>>>>>>> >>>>>>>> I want to use E310 as multi channel transmitter and receiver and >>>>>>>> want to test it using signal generator and oscilloscope. >>>>>>>> >>>>>>>> I tried to import the code from usrp3/top/e300 subdirectory into >>>>>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize it. >>>>>>>> >>>>>>>> Can you explain me step by step, how to work with E310. >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> *Thanks !!* >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer < >>>>>>>> moritz.fischer@ettus.com> wrote: >>>>>>>> >>>>>>>>> Hi Bhushan, >>>>>>>>> >>>>>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >>>>>>>>> <usrp-users@lists.ettus.com> wrote: >>>>>>>>> > Hello, >>>>>>>>> > >>>>>>>>> > I am trying to build multi channel transmitter and receiver >>>>>>>>> using USRP E310. >>>>>>>>> >>>>>>>>> all our code for E310 is open-source. Feel free to peruse our >>>>>>>>> github. >>>>>>>>> On the FPGA side you might wanna look at the usrp3/top/e300 >>>>>>>>> subdirectory [1]. >>>>>>>>> >>>>>>>>> If you let us know what exactly you're trying to do, people can >>>>>>>>> help >>>>>>>>> you out easier. >>>>>>>>> > However I am new to FPGA programming, hence I am facing a lot of >>>>>>>>> challenges >>>>>>>>> > in interfacing ZynQ board with the transceiver and filter banks >>>>>>>>> in Vivado >>>>>>>>> > 2015.4. >>>>>>>>> > Is to possible to get few demo projects which might help me to >>>>>>>>> understand >>>>>>>>> > the data flow in the simple transmitter and receiver >>>>>>>>> application? Kindly >>>>>>>>> > share few useful documents which will help me to understand the >>>>>>>>> above >>>>>>>>> > problem. >>>>>>>>> >>>>>>>>> Again, all our code for E310 is open source (apart from Xilinx IP). >>>>>>>>> Feel free to dig through the code. >>>>>>>>> The filter bank settings are documented in the UHD manual [2]. >>>>>>>>> >>>>>>>>> Good luck, >>>>>>>>> >>>>>>>>> Moritz >>>>>>>>> >>>>>>>>> [1] >>>>>>>>> https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >>>>>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >>>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> _______________________________________________ >>>>>>>> USRP-users mailing list >>>>>>>> USRP-users@lists.ettus.com >>>>>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>>>>>> >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >

Dear Jonathon, Thanks for your reply. I followed your suggestion and and to build the project using command 'make E310 GUI=1'. It opened the GUI for Vivado, however before I could save the project there was an error and Vivado was closed automatically. Below are the lines from terminal also I am attaching the log file with this email, [pawa_bh@ohff24 e300]$ chmod u+x setupenv.sh [pawa_bh@ohff24 e300]$ . setupenv.sh Setting up X3x0 FPGA build environment (64-bit)... bash: /opt/Xilinx/Vivado_HLS/Vivado/2014.4/.settings64-Vivado_High_Level_Synthesis.sh: Datei oder Verzeichnis nicht gefunden - Vivado: Found (/opt/Xilinx/Vivado/Vivado/2014.4/bin) Environment successfully initialized. [pawa_bh@ohff24 e300]$ make E310 GUI=1 make -f Makefile.e300.inc bin NAME=E310 ARCH=zynq PART_ID=xc7z020/clg484/-1 EXTRA_DEFS="E310" make[1]: Entering directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300' Vivado v2014.4 (64-bit) ****** Vivado v2014.4 (64-bit) **** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014 **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. start_gui Abnormal program termination (11) Please check '/home/pawa_bh/uhd/fpga-src/usrp3/top/e300/build-E310/hs_err_pid12758.log' for details make[1]: *** [bin] Fehler 139 make[1]: Leaving directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300' make: *** [E310] Fehler 2 [pawa_bh@ohff24 e300]$ I tried building the project with only make E310 command and the bit file was generated without any error. Kindly help me to resolve this issue. *Thanks & Regards,* *Bhushan R.V. Pawar.* *(+49-17685263152)* On Wed, Apr 20, 2016 at 11:39 AM, BHUSHAN PAWAR <bhushan.rv.pawar@gmail.com> wrote: > Dear Jonathon, > > Thanks for your reply. I followed your suggestion and and to build the > project using command 'make E310 GUI=1'. > It opened the GUI for Vivado, however before I could save the project > there was an error and Vivado was closed automatically. Below are the lines > from terminal also I am attaching the log file with this email, > > [pawa_bh@ohff24 e300]$ chmod u+x setupenv.sh > [pawa_bh@ohff24 e300]$ . setupenv.sh > Setting up X3x0 FPGA build environment (64-bit)... > bash: > /opt/Xilinx/Vivado_HLS/Vivado/2014.4/.settings64-Vivado_High_Level_Synthesis.sh: > Datei oder Verzeichnis nicht gefunden > - Vivado: Found (/opt/Xilinx/Vivado/Vivado/2014.4/bin) > > Environment successfully initialized. > [pawa_bh@ohff24 e300]$ make E310 GUI=1 > make -f Makefile.e300.inc bin NAME=E310 ARCH=zynq > PART_ID=xc7z020/clg484/-1 EXTRA_DEFS="E310" > make[1]: Entering directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300' > Vivado v2014.4 (64-bit) > > ****** Vivado v2014.4 (64-bit) > **** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014 > **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 > ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. > > start_gui > Abnormal program termination (11) > Please check > '/home/pawa_bh/uhd/fpga-src/usrp3/top/e300/build-E310/hs_err_pid12758.log' > for details > make[1]: *** [bin] Fehler 139 > make[1]: Leaving directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300' > make: *** [E310] Fehler 2 > [pawa_bh@ohff24 e300]$ > > > I tried building the project with only make E310 command and the bit file > was generated without any error. > Kindly help me to resolve this issue. > > > *Thanks & Regards,* > > *Bhushan R.V. Pawar.* > > > On Mon, Feb 15, 2016 at 11:14 PM, Jonathon Pendlum < > jonathon.pendlum@ettus.com> wrote: > >> Hi Pawar, >> >> It looks like you created a Vivado project file and then manually >> imported source files. I would suggest instead running make with GUI=1, >> i.e. make GUI=1 E310. This will load the Vivado GUI and you can save a >> project file from there (File->Save Project As...). >> >> >> >> Jonathon >> >> On Mon, Feb 15, 2016 at 8:05 AM, Nikos Balkanas via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> Hi, >>> >>> Did you followed the Makefile procedure indicated by James? What target >>> did you build? >>> >>> Nikos >>> >>> On Mon, Feb 15, 2016 at 5:26 PM, BHUSHAN PAWAR < >>> bhushan.rv.pawar@gmail.com> wrote: >>> >>>> Errors: >>>> >>>> [Synthv8-448] named port connection 'GPIO_I' does not exist for >>>> instance 'inst_processing_system7' of module 'processing_system7_1' >>>> [e3xx_ps.v.263] >>>> (85 more like this) >>>> >>>> [Synthv8-285] failed synthesizing module 'axi4_fifo_512x64' >>>> [axi4_fifo_512x64_stub.v.7] >>>> (2 more like this) >>>> >>>> *Thanks & Regards,* >>>> >>>> *Bhushan R.V. Pawar.* >>>> *(+49-17685263152 <%28%2B49-17685263152>)* >>>> >>>> >>>> On Mon, Feb 15, 2016 at 4:08 PM, BHUSHAN PAWAR < >>>> bhushan.rv.pawar@gmail.com> wrote: >>>> >>>>> Hi all, >>>>> >>>>> I am using the source code from Github usrp3/top/e300 and trying to >>>>> synthesize the code. However, I am getting these errors. Kindly help. >>>>> >>>>> [image: Inline image 2][image: Inline image 1] >>>>> >>>>> >>>>> *Thanks !!* >>>>> >>>>> >>>>> On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <nbalkanas@gmail.com> >>>>> wrote: >>>>> >>>>>> Hi Pawar, >>>>>> >>>>>> The FPGA sources are to modify the FPGA. The FPGA is larger than the >>>>>> image it currently holds. Many people use it to add aditional filters, >>>>>> FFTs, etc. >>>>>> Adding on top of what already exists and is needed for correct >>>>>> functionality...But you need to know Vivado for that. Check also RFNOC, it >>>>>> may be easier:) >>>>>> >>>>>> PS: Plz keep discussion in group, so that others may benefit as >>>>>> well... >>>>>> >>>>>> HTH, >>>>>> Nikos >>>>>> >>>>>> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR < >>>>>> bhushan.rv.pawar@gmail.com> wrote: >>>>>> >>>>>>> Hi Nikos, >>>>>>> >>>>>>> Thanks for the reply. >>>>>>> >>>>>>> Then can you explain me what is the real use of the FPGA code on >>>>>>> usrp3/top/e300 subdirectory on github. >>>>>>> >>>>>>> How can I use this code to get started? >>>>>>> >>>>>>> >>>>>>> >>>>>>> *Thanks & Regards,* >>>>>>> >>>>>>> *Bhushan R.V. Pawar.* >>>>>>> >>>>>>> >>>>>>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas < >>>>>>> nbalkanas@gmail.com> wrote: >>>>>>> >>>>>>>> Hi, >>>>>>>> >>>>>>>> Have you also tried vivado forums? They can help more than what we >>>>>>>> can here... >>>>>>>> Plz post your errors. Recently started on vivado myself, and the >>>>>>>> only errors I got were from licensing issues for my FPGA. >>>>>>>> I have an X300 >>>>>>>> >>>>>>>> HTH, >>>>>>>> Nikos >>>>>>>> >>>>>>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < >>>>>>>> usrp-users@lists.ettus.com> wrote: >>>>>>>> >>>>>>>>> Dear Moritz, >>>>>>>>> >>>>>>>>> Thank you for the reply. >>>>>>>>> >>>>>>>>> I want to use E310 as multi channel transmitter and receiver and >>>>>>>>> want to test it using signal generator and oscilloscope. >>>>>>>>> >>>>>>>>> I tried to import the code from usrp3/top/e300 subdirectory into >>>>>>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize it. >>>>>>>>> >>>>>>>>> Can you explain me step by step, how to work with E310. >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>> *Thanks !!* >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer < >>>>>>>>> moritz.fischer@ettus.com> wrote: >>>>>>>>> >>>>>>>>>> Hi Bhushan, >>>>>>>>>> >>>>>>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >>>>>>>>>> <usrp-users@lists.ettus.com> wrote: >>>>>>>>>> > Hello, >>>>>>>>>> > >>>>>>>>>> > I am trying to build multi channel transmitter and receiver >>>>>>>>>> using USRP E310. >>>>>>>>>> >>>>>>>>>> all our code for E310 is open-source. Feel free to peruse our >>>>>>>>>> github. >>>>>>>>>> On the FPGA side you might wanna look at the usrp3/top/e300 >>>>>>>>>> subdirectory [1]. >>>>>>>>>> >>>>>>>>>> If you let us know what exactly you're trying to do, people can >>>>>>>>>> help >>>>>>>>>> you out easier. >>>>>>>>>> > However I am new to FPGA programming, hence I am facing a lot >>>>>>>>>> of challenges >>>>>>>>>> > in interfacing ZynQ board with the transceiver and filter banks >>>>>>>>>> in Vivado >>>>>>>>>> > 2015.4. >>>>>>>>>> > Is to possible to get few demo projects which might help me to >>>>>>>>>> understand >>>>>>>>>> > the data flow in the simple transmitter and receiver >>>>>>>>>> application? Kindly >>>>>>>>>> > share few useful documents which will help me to understand the >>>>>>>>>> above >>>>>>>>>> > problem. >>>>>>>>>> >>>>>>>>>> Again, all our code for E310 is open source (apart from Xilinx >>>>>>>>>> IP). >>>>>>>>>> Feel free to dig through the code. >>>>>>>>>> The filter bank settings are documented in the UHD manual [2]. >>>>>>>>>> >>>>>>>>>> Good luck, >>>>>>>>>> >>>>>>>>>> Moritz >>>>>>>>>> >>>>>>>>>> [1] >>>>>>>>>> https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >>>>>>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >>>>>>>>>> >>>>>>>>> >>>>>>>>> >>>>>>>>> _______________________________________________ >>>>>>>>> USRP-users mailing list >>>>>>>>> USRP-users@lists.ettus.com >>>>>>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>>>>>>> >>>>>>>>> >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >> >

Hi, It looks like a problem with Vivado itself. Are you using one of the support OSs (see http://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_4/ug973-vivado-release-notes-install-license.pdf)? Can you create a project with the GUI outside of our flow? Jonathon On Wed, Apr 20, 2016 at 2:45 AM, BHUSHAN PAWAR <bhushan.rv.pawar@gmail.com> wrote: > Dear Jonathon, > > Thanks for your reply. I followed your suggestion and and to build the > project using command 'make E310 GUI=1'. > It opened the GUI for Vivado, however before I could save the project > there was an error and Vivado was closed automatically. Below are the lines > from terminal also I am attaching the log file with this email, > > [pawa_bh@ohff24 e300]$ chmod u+x setupenv.sh > [pawa_bh@ohff24 e300]$ . setupenv.sh > Setting up X3x0 FPGA build environment (64-bit)... > bash: > /opt/Xilinx/Vivado_HLS/Vivado/2014.4/.settings64-Vivado_High_Level_Synthesis.sh: > Datei oder Verzeichnis nicht gefunden > - Vivado: Found (/opt/Xilinx/Vivado/Vivado/2014.4/bin) > > Environment successfully initialized. > [pawa_bh@ohff24 e300]$ make E310 GUI=1 > make -f Makefile.e300.inc bin NAME=E310 ARCH=zynq > PART_ID=xc7z020/clg484/-1 EXTRA_DEFS="E310" > make[1]: Entering directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300' > Vivado v2014.4 (64-bit) > > ****** Vivado v2014.4 (64-bit) > **** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014 > **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 > ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. > > start_gui > Abnormal program termination (11) > Please check '/home/pawa_bh/uhd/fpga-src/usrp3/top/e300/build-E310/hs_err_pid12758.log' > for details > make[1]: *** [bin] Fehler 139 > make[1]: Leaving directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300' > make: *** [E310] Fehler 2 > [pawa_bh@ohff24 e300]$ > > > I tried building the project with only make E310 command and the bit file > was generated without any error. > Kindly help me to resolve this issue. > > *Thanks & Regards,* > > *Bhushan R.V. Pawar.* > *(+49-17685263152 <%28%2B49-17685263152>)* > > > On Wed, Apr 20, 2016 at 11:39 AM, BHUSHAN PAWAR < > bhushan.rv.pawar@gmail.com> wrote: > >> Dear Jonathon, >> >> Thanks for your reply. I followed your suggestion and and to build the >> project using command 'make E310 GUI=1'. >> It opened the GUI for Vivado, however before I could save the project >> there was an error and Vivado was closed automatically. Below are the lines >> from terminal also I am attaching the log file with this email, >> >> [pawa_bh@ohff24 e300]$ chmod u+x setupenv.sh >> [pawa_bh@ohff24 e300]$ . setupenv.sh >> Setting up X3x0 FPGA build environment (64-bit)... >> bash: >> /opt/Xilinx/Vivado_HLS/Vivado/2014.4/.settings64-Vivado_High_Level_Synthesis.sh: >> Datei oder Verzeichnis nicht gefunden >> - Vivado: Found (/opt/Xilinx/Vivado/Vivado/2014.4/bin) >> >> Environment successfully initialized. >> [pawa_bh@ohff24 e300]$ make E310 GUI=1 >> make -f Makefile.e300.inc bin NAME=E310 ARCH=zynq >> PART_ID=xc7z020/clg484/-1 EXTRA_DEFS="E310" >> make[1]: Entering directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300' >> Vivado v2014.4 (64-bit) >> >> ****** Vivado v2014.4 (64-bit) >> **** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014 >> **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014 >> ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. >> >> start_gui >> Abnormal program termination (11) >> Please check >> '/home/pawa_bh/uhd/fpga-src/usrp3/top/e300/build-E310/hs_err_pid12758.log' >> for details >> make[1]: *** [bin] Fehler 139 >> make[1]: Leaving directory `/home/pawa_bh/uhd/fpga-src/usrp3/top/e300' >> make: *** [E310] Fehler 2 >> [pawa_bh@ohff24 e300]$ >> >> >> I tried building the project with only make E310 command and the bit file >> was generated without any error. >> Kindly help me to resolve this issue. >> >> >> *Thanks & Regards,* >> >> *Bhushan R.V. Pawar.* >> >> >> On Mon, Feb 15, 2016 at 11:14 PM, Jonathon Pendlum < >> jonathon.pendlum@ettus.com> wrote: >> >>> Hi Pawar, >>> >>> It looks like you created a Vivado project file and then manually >>> imported source files. I would suggest instead running make with GUI=1, >>> i.e. make GUI=1 E310. This will load the Vivado GUI and you can save a >>> project file from there (File->Save Project As...). >>> >>> >>> >>> Jonathon >>> >>> On Mon, Feb 15, 2016 at 8:05 AM, Nikos Balkanas via USRP-users < >>> usrp-users@lists.ettus.com> wrote: >>> >>>> Hi, >>>> >>>> Did you followed the Makefile procedure indicated by James? What target >>>> did you build? >>>> >>>> Nikos >>>> >>>> On Mon, Feb 15, 2016 at 5:26 PM, BHUSHAN PAWAR < >>>> bhushan.rv.pawar@gmail.com> wrote: >>>> >>>>> Errors: >>>>> >>>>> [Synthv8-448] named port connection 'GPIO_I' does not exist for >>>>> instance 'inst_processing_system7' of module 'processing_system7_1' >>>>> [e3xx_ps.v.263] >>>>> (85 more like this) >>>>> >>>>> [Synthv8-285] failed synthesizing module 'axi4_fifo_512x64' >>>>> [axi4_fifo_512x64_stub.v.7] >>>>> (2 more like this) >>>>> >>>>> *Thanks & Regards,* >>>>> >>>>> *Bhushan R.V. Pawar.* >>>>> *(+49-17685263152 <%28%2B49-17685263152>)* >>>>> >>>>> >>>>> On Mon, Feb 15, 2016 at 4:08 PM, BHUSHAN PAWAR < >>>>> bhushan.rv.pawar@gmail.com> wrote: >>>>> >>>>>> Hi all, >>>>>> >>>>>> I am using the source code from Github usrp3/top/e300 and trying to >>>>>> synthesize the code. However, I am getting these errors. Kindly help. >>>>>> >>>>>> [image: Inline image 2][image: Inline image 1] >>>>>> >>>>>> >>>>>> *Thanks !!* >>>>>> >>>>>> >>>>>> On Mon, Feb 15, 2016 at 1:22 PM, Nikos Balkanas <nbalkanas@gmail.com> >>>>>> wrote: >>>>>> >>>>>>> Hi Pawar, >>>>>>> >>>>>>> The FPGA sources are to modify the FPGA. The FPGA is larger than the >>>>>>> image it currently holds. Many people use it to add aditional filters, >>>>>>> FFTs, etc. >>>>>>> Adding on top of what already exists and is needed for correct >>>>>>> functionality...But you need to know Vivado for that. Check also RFNOC, it >>>>>>> may be easier:) >>>>>>> >>>>>>> PS: Plz keep discussion in group, so that others may benefit as >>>>>>> well... >>>>>>> >>>>>>> HTH, >>>>>>> Nikos >>>>>>> >>>>>>> On Mon, Feb 15, 2016 at 2:11 PM, BHUSHAN PAWAR < >>>>>>> bhushan.rv.pawar@gmail.com> wrote: >>>>>>> >>>>>>>> Hi Nikos, >>>>>>>> >>>>>>>> Thanks for the reply. >>>>>>>> >>>>>>>> Then can you explain me what is the real use of the FPGA code on >>>>>>>> usrp3/top/e300 subdirectory on github. >>>>>>>> >>>>>>>> How can I use this code to get started? >>>>>>>> >>>>>>>> >>>>>>>> >>>>>>>> *Thanks & Regards,* >>>>>>>> >>>>>>>> *Bhushan R.V. Pawar.* >>>>>>>> >>>>>>>> >>>>>>>> On Mon, Feb 15, 2016 at 12:06 PM, Nikos Balkanas < >>>>>>>> nbalkanas@gmail.com> wrote: >>>>>>>> >>>>>>>>> Hi, >>>>>>>>> >>>>>>>>> Have you also tried vivado forums? They can help more than what we >>>>>>>>> can here... >>>>>>>>> Plz post your errors. Recently started on vivado myself, and the >>>>>>>>> only errors I got were from licensing issues for my FPGA. >>>>>>>>> I have an X300 >>>>>>>>> >>>>>>>>> HTH, >>>>>>>>> Nikos >>>>>>>>> >>>>>>>>> On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < >>>>>>>>> usrp-users@lists.ettus.com> wrote: >>>>>>>>> >>>>>>>>>> Dear Moritz, >>>>>>>>>> >>>>>>>>>> Thank you for the reply. >>>>>>>>>> >>>>>>>>>> I want to use E310 as multi channel transmitter and receiver and >>>>>>>>>> want to test it using signal generator and oscilloscope. >>>>>>>>>> >>>>>>>>>> I tried to import the code from usrp3/top/e300 subdirectory into >>>>>>>>>> Vivado 2015.4 but it is giving many errors when I try to synthesize it. >>>>>>>>>> >>>>>>>>>> Can you explain me step by step, how to work with E310. >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> *Thanks !!* >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer < >>>>>>>>>> moritz.fischer@ettus.com> wrote: >>>>>>>>>> >>>>>>>>>>> Hi Bhushan, >>>>>>>>>>> >>>>>>>>>>> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >>>>>>>>>>> <usrp-users@lists.ettus.com> wrote: >>>>>>>>>>> > Hello, >>>>>>>>>>> > >>>>>>>>>>> > I am trying to build multi channel transmitter and receiver >>>>>>>>>>> using USRP E310. >>>>>>>>>>> >>>>>>>>>>> all our code for E310 is open-source. Feel free to peruse our >>>>>>>>>>> github. >>>>>>>>>>> On the FPGA side you might wanna look at the usrp3/top/e300 >>>>>>>>>>> subdirectory [1]. >>>>>>>>>>> >>>>>>>>>>> If you let us know what exactly you're trying to do, people can >>>>>>>>>>> help >>>>>>>>>>> you out easier. >>>>>>>>>>> > However I am new to FPGA programming, hence I am facing a lot >>>>>>>>>>> of challenges >>>>>>>>>>> > in interfacing ZynQ board with the transceiver and filter >>>>>>>>>>> banks in Vivado >>>>>>>>>>> > 2015.4. >>>>>>>>>>> > Is to possible to get few demo projects which might help me to >>>>>>>>>>> understand >>>>>>>>>>> > the data flow in the simple transmitter and receiver >>>>>>>>>>> application? Kindly >>>>>>>>>>> > share few useful documents which will help me to understand >>>>>>>>>>> the above >>>>>>>>>>> > problem. >>>>>>>>>>> >>>>>>>>>>> Again, all our code for E310 is open source (apart from Xilinx >>>>>>>>>>> IP). >>>>>>>>>>> Feel free to dig through the code. >>>>>>>>>>> The filter bank settings are documented in the UHD manual [2]. >>>>>>>>>>> >>>>>>>>>>> Good luck, >>>>>>>>>>> >>>>>>>>>>> Moritz >>>>>>>>>>> >>>>>>>>>>> [1] >>>>>>>>>>> https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >>>>>>>>>>> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >>>>>>>>>>> >>>>>>>>>> >>>>>>>>>> >>>>>>>>>> _______________________________________________ >>>>>>>>>> USRP-users mailing list >>>>>>>>>> USRP-users@lists.ettus.com >>>>>>>>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>>>>>>>> >>>>>>>>>> >>>>>>>>> >>>>>>>> >>>>>>> >>>>>> >>>>> >>>> >>>> _______________________________________________ >>>> USRP-users mailing list >>>> USRP-users@lists.ettus.com >>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>> >>>> >>> >> >