My first Swainson's in the yard and he was going from tops of hemlocks to mid to top of oak. The song alerted me and I got a couple good views. Very happy to hear that beautiful song.

Not immediately recognized as White-crowned, but when seeing picture with top of head clear, positively identified: white on top of head, *wide* bright white, no yellow spot, whitish throat, but not like WTSP. > > View this checklist online at https://ebird.org/view/checklist/S54816940 > > This report was generated automatically by eBird v3 (https://ebird.org

/x300/bus_int.v:9] ERROR: [Synth 8-6156] failed synthesizing module 'x300_core' [/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x300_core.v:9] ERROR: [Synth 8-6156] failed synthesizing module 'x300' [/home/sp/Documents/uhd-4.1.0.5/fpga/usrp3/top/x300/x300.v:20] ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file

For the SVG file, the top left angle > is at 0,0. > > When imported with import(“A4.svg“), OpenScad uses pixel units as is, > and millimeters from the svg file are converted to pixels at 96 dpi. > So it draws a rectangle of 793.7×1122.5. But it puts the top left > angle at coordinates 0,396.

-verilog_define RFNOC_IMAGE_CORE_HDR=x410_200_rfnoc_image_core.vh -verilog_define UHD_FPGA_DIR=/home/user/RFSoC/uhd/fpga/usrp3/top/../.

That gets straight teeth, but I am also looking to be able to set the bevel gear on top of a spur gear.

The default slicer > settings [for Cura], always need tweaking, I use a minimum of 3 walls > and 1.2mm [ish] top and bottom layers, the infill pattern depends on the > model, too thin walls causes the infill to influence the outer wall > finish and no enough top and bottom layers means there could be > incomplete surface finishes - but that could just be my printers

.\ \ If you trace the \`radio_tx_stb\` back to where it is assigned in x4xx.sv, it seems to be assigned based on the \`dac_data_in_tready\` signals: * X410: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x400/x4xx.sv#L2685 * X440: https://github.com/EttusResearch/uhd/blob/master/fpga/usrp3/top/x400/x4xx.sv#L2664 As I understand the \`radio_tx_stb

I really should have said "top-level", names like these: TOP = 5; module xrot(); function scale() = 3; Because BOSL2 is include<>d (for mostly good reasons), and because OpenSCAD lets the main program silently override names from the include<>d file, the result of such conflicts will be ... chaos.

/x300/build-ip/ten_gig_eth_pcs_pma >> make[1]: *** >> [/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] >> Error 1 >> make[1]: Leaving directory >> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' >> make: *** [X310_RFNOC_HG] Error 2 >> >> -----------------------------------------------------------------