Dear Jonathon, I tried what you told me. First, I ran setupenv.sh and then executed make X310_RFNOC_HG. The bistream was successfully generated as you can see by the messages below. Creating bitstream... Writing bitstream /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/x300.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. And again, it has the same size, 15878034, as the other bitstream I generated with 2xDDCs, 2xDUCs and 1xFFT. -rw-rw-r-- 1 zz4fap zz4fap 15878034 Feb 27 22:47 x300.bit Could you, please, check why this difference exists? I mean, the difference of 2 bytes between bitstreams. While cheking the Makefile at src/uhd-fpga/usrp3/top/x300 I read what I think could be a clue to the problem: ## build/usrp_<product>_fpga_<image_type>.bit: Configuration bitstream with header ## build/usrp_<product>_fpga_<image_type>.bin: Configuration bitstream without header May the 2 bytes longer bitstream (.bit) contains a 2 bytes long header. Thanks and Best Regards, Felipe On Mon, Feb 27, 2017 at 9:07 PM, Jonathon Pendlum <jonathon.pendlum@ettus.com> wrote: > Hi Felipe, > > Make sure to run 'source setupenv.sh' first before make X310_RFNOC_HG > > On Mon, Feb 27, 2017 at 1:31 PM, Felipe Augusto Pereira de Figueiredo > <zz4fap@gmail.com> wrote: >> >> Hi Jonathon, >> >> Tried what you said but it didn't work. Could you please be a little >> bit more specific about the command I should run. I got some error >> regarding the syntax of the command you told me to run. >> See output below. >> >> Thanks and Best Regards, >> >> Felipe >> >> >> --------------------------------------------------------------------------------------------------------------------------------------------------------- >> zz4fap@imecdesktop:~/rfnoc/src/uhd-fpga/usrp3/top/x300$ make X310_RFNOC_HG >> make -f Makefile.x300.inc bin NAME=X310_RFNOC_HG ARCH= PART_ID= >> BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 >> EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 >> X310=1" >> find: >> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/addsub_hls/solution/impl/verilog/': >> No such file or directory >> make[1]: Entering directory >> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' >> BUILDER: Checking tools... >> * GNU bash, version 4.3.11(1)-release (x86_64-pc-linux-gnu) >> * Python 2.7.6 >> * Vivado v2015.4.2 (64-bit) >> ======================================================== >> BUILDER: Building IP ten_gig_eth_pcs_pma >> ======================================================== >> BUILDER: Staging IP in build directory... >> BUILDER: Reserving IP location: >> >> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_gig_eth_pcs_pma >> BUILDER: Retargeting IP to part /... >> ERROR: Invalid target format. Must be >> <arch>/<device>/<package>/<speedgrade> >> BUILDER: Building IP... >> >> ****** Vivado v2015.4.2 (64-bit) >> **** SW Build 1494164 on Fri Feb 26 04:18:54 MST 2016 >> **** IP Build 1491208 on Wed Feb 24 03:25:39 MST 2016 >> ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. >> >> source >> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_generate_ip.tcl >> # set xci_file $::env(XCI_FILE) ; >> # set part_name $::env(PART_NAME) ; >> # set gen_example_proj $::env(GEN_EXAMPLE) ; >> # set synth_ip $::env(SYNTH_IP) ; >> # set ip_name [file rootname [file tail $xci_file]] ; >> # file delete -force "$xci_file.out" >> # create_project -part $part_name -in_memory -ip >> WARNING: [#UNDEF] No parts matched '' >> ERROR: [Coretcl 2-106] Specified part could not be found. >> INFO: [Common 17-206] Exiting Vivado at Mon Feb 27 20:26:39 2017... >> BUILDER: Releasing IP location: >> >> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_gig_eth_pcs_pma >> make[1]: *** >> [/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] >> Error 1 >> make[1]: Leaving directory >> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' >> make: *** [X310_RFNOC_HG] Error 2 >> >> --------------------------------------------------------------------------------------------------------------------------------------------------------- >> >> On Mon, Feb 27, 2017 at 7:55 PM, Jonathon Pendlum >> <jonathon.pendlum@ettus.com> wrote: >> > Hi Felipe, >> > >> > What if you build the same image by running make X310_RFNOC_HG in >> > usrp3/top/x300? Is it still too large? >> > >> > On Mon, Feb 27, 2017 at 4:23 AM, Felipe Augusto Pereira de Figueiredo >> > via >> > USRP-users <usrp-users@lists.ettus.com> wrote: >> >> >> >> Dear Sam, >> >> >> >> Many thanks for your tip, I've followed that and it worked. Just >> >> changed the size of the macro with the expected bitstream size. >> >> >> >> I hope someone from Ettus can explain why that problem happens and if >> >> it can be solved other way instead of tweaking the source code. >> >> >> >> Now the output of "uhd_usrp_probe" is like I had expected it to be. >> >> >> >> | | _____________________________________________________ >> >> | | / >> >> | | | RFNoC blocks on this device: >> >> | | | >> >> | | | * DmaFIFO_0 >> >> | | | * Radio_0 >> >> | | | * Radio_1 >> >> | | | * DDC_0 >> >> | | | * DDC_1 >> >> | | | * DUC_0 >> >> | | | * DUC_1 >> >> | | | * FFT_0 >> >> >> >> Thanks and Best Regards, >> >> >> >> Felipe >> >> >> >> On Fri, Feb 24, 2017 at 3:27 PM, Sam Carey <sam@samcarey.com> wrote: >> >> > Howdy, >> >> > >> >> > I had this problem a while back. My workaround was to simply edit the >> >> > image >> >> > loader code so that it is OK with the larger file size. >> >> > Just do a search for the smaller byte number in the uhd/host source >> >> > code, >> >> > change it to the larger byte number, and rebuild/reinstall uhd. >> >> > Apparently, the byte count is not a strict requirement for image >> >> > loading. >> >> > >> >> > You're the second other person I've seen with this problem. >> >> > Maybe somebody could apply this change to the main branch or >> >> > something? >> >> > >> >> > -Sam >> >> > >> >> > >> >> >> >> _______________________________________________ >> >> USRP-users mailing list >> >> USRP-users@lists.ettus.com >> >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > >> > > >

Dear Jonathon, Do you have any update on the 2 bytes larger bitstream issue? I was expecting someone from ettus to give us an explanation on that and if it is an issue. Thanks and Best Regards, Felipe Augusto On Tue, Feb 28, 2017 at 9:43 AM, Felipe Augusto Pereira de Figueiredo <zz4fap@gmail.com> wrote: > Dear Jonathon, > > I tried what you told me. First, I ran setupenv.sh and then executed > make X310_RFNOC_HG. > > The bistream was successfully generated as you can see by the messages below. > > Creating bitstream... > Writing bitstream > /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/x300.bit... > INFO: [Vivado 12-1842] Bitgen Completed Successfully. > > And again, it has the same size, 15878034, as the other bitstream I > generated with 2xDDCs, 2xDUCs and 1xFFT. > > -rw-rw-r-- 1 zz4fap zz4fap 15878034 Feb 27 22:47 x300.bit > > Could you, please, check why this difference exists? I mean, the > difference of 2 bytes between bitstreams. > > While cheking the Makefile at src/uhd-fpga/usrp3/top/x300 I read what > I think could be a clue to the problem: > > ## build/usrp_<product>_fpga_<image_type>.bit: Configuration > bitstream with header > ## build/usrp_<product>_fpga_<image_type>.bin: Configuration > bitstream without header > > May the 2 bytes longer bitstream (.bit) contains a 2 bytes long header. > > Thanks and Best Regards, > > Felipe > > On Mon, Feb 27, 2017 at 9:07 PM, Jonathon Pendlum > <jonathon.pendlum@ettus.com> wrote: >> Hi Felipe, >> >> Make sure to run 'source setupenv.sh' first before make X310_RFNOC_HG >> >> On Mon, Feb 27, 2017 at 1:31 PM, Felipe Augusto Pereira de Figueiredo >> <zz4fap@gmail.com> wrote: >>> >>> Hi Jonathon, >>> >>> Tried what you said but it didn't work. Could you please be a little >>> bit more specific about the command I should run. I got some error >>> regarding the syntax of the command you told me to run. >>> See output below. >>> >>> Thanks and Best Regards, >>> >>> Felipe >>> >>> >>> --------------------------------------------------------------------------------------------------------------------------------------------------------- >>> zz4fap@imecdesktop:~/rfnoc/src/uhd-fpga/usrp3/top/x300$ make X310_RFNOC_HG >>> make -f Makefile.x300.inc bin NAME=X310_RFNOC_HG ARCH= PART_ID= >>> BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 >>> EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 >>> X310=1" >>> find: >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/addsub_hls/solution/impl/verilog/': >>> No such file or directory >>> make[1]: Entering directory >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' >>> BUILDER: Checking tools... >>> * GNU bash, version 4.3.11(1)-release (x86_64-pc-linux-gnu) >>> * Python 2.7.6 >>> * Vivado v2015.4.2 (64-bit) >>> ======================================================== >>> BUILDER: Building IP ten_gig_eth_pcs_pma >>> ======================================================== >>> BUILDER: Staging IP in build directory... >>> BUILDER: Reserving IP location: >>> >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_gig_eth_pcs_pma >>> BUILDER: Retargeting IP to part /... >>> ERROR: Invalid target format. Must be >>> <arch>/<device>/<package>/<speedgrade> >>> BUILDER: Building IP... >>> >>> ****** Vivado v2015.4.2 (64-bit) >>> **** SW Build 1494164 on Fri Feb 26 04:18:54 MST 2016 >>> **** IP Build 1491208 on Wed Feb 24 03:25:39 MST 2016 >>> ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. >>> >>> source >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_generate_ip.tcl >>> # set xci_file $::env(XCI_FILE) ; >>> # set part_name $::env(PART_NAME) ; >>> # set gen_example_proj $::env(GEN_EXAMPLE) ; >>> # set synth_ip $::env(SYNTH_IP) ; >>> # set ip_name [file rootname [file tail $xci_file]] ; >>> # file delete -force "$xci_file.out" >>> # create_project -part $part_name -in_memory -ip >>> WARNING: [#UNDEF] No parts matched '' >>> ERROR: [Coretcl 2-106] Specified part could not be found. >>> INFO: [Common 17-206] Exiting Vivado at Mon Feb 27 20:26:39 2017... >>> BUILDER: Releasing IP location: >>> >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_gig_eth_pcs_pma >>> make[1]: *** >>> [/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] >>> Error 1 >>> make[1]: Leaving directory >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' >>> make: *** [X310_RFNOC_HG] Error 2 >>> >>> --------------------------------------------------------------------------------------------------------------------------------------------------------- >>> >>> On Mon, Feb 27, 2017 at 7:55 PM, Jonathon Pendlum >>> <jonathon.pendlum@ettus.com> wrote: >>> > Hi Felipe, >>> > >>> > What if you build the same image by running make X310_RFNOC_HG in >>> > usrp3/top/x300? Is it still too large? >>> > >>> > On Mon, Feb 27, 2017 at 4:23 AM, Felipe Augusto Pereira de Figueiredo >>> > via >>> > USRP-users <usrp-users@lists.ettus.com> wrote: >>> >> >>> >> Dear Sam, >>> >> >>> >> Many thanks for your tip, I've followed that and it worked. Just >>> >> changed the size of the macro with the expected bitstream size. >>> >> >>> >> I hope someone from Ettus can explain why that problem happens and if >>> >> it can be solved other way instead of tweaking the source code. >>> >> >>> >> Now the output of "uhd_usrp_probe" is like I had expected it to be. >>> >> >>> >> | | _____________________________________________________ >>> >> | | / >>> >> | | | RFNoC blocks on this device: >>> >> | | | >>> >> | | | * DmaFIFO_0 >>> >> | | | * Radio_0 >>> >> | | | * Radio_1 >>> >> | | | * DDC_0 >>> >> | | | * DDC_1 >>> >> | | | * DUC_0 >>> >> | | | * DUC_1 >>> >> | | | * FFT_0 >>> >> >>> >> Thanks and Best Regards, >>> >> >>> >> Felipe >>> >> >>> >> On Fri, Feb 24, 2017 at 3:27 PM, Sam Carey <sam@samcarey.com> wrote: >>> >> > Howdy, >>> >> > >>> >> > I had this problem a while back. My workaround was to simply edit the >>> >> > image >>> >> > loader code so that it is OK with the larger file size. >>> >> > Just do a search for the smaller byte number in the uhd/host source >>> >> > code, >>> >> > change it to the larger byte number, and rebuild/reinstall uhd. >>> >> > Apparently, the byte count is not a strict requirement for image >>> >> > loading. >>> >> > >>> >> > You're the second other person I've seen with this problem. >>> >> > Maybe somebody could apply this change to the main branch or >>> >> > something? >>> >> > >>> >> > -Sam >>> >> > >>> >> > >>> >> >>> >> _______________________________________________ >>> >> USRP-users mailing list >>> >> USRP-users@lists.ettus.com >>> >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> > >>> > >> >>

Hi Felipe, I do not currently have an explanation why the Xilinx tools generate a bitstream with a different file size. When I run your build command, the output bitstream size is 15878032. What OS / Xilinx tools are you building with? Jonathon On Thu, Mar 2, 2017 at 11:07 AM, Felipe Augusto Pereira de Figueiredo < zz4fap@gmail.com> wrote: > Dear Jonathon, > > Do you have any update on the 2 bytes larger bitstream issue? > > I was expecting someone from ettus to give us an explanation on that > and if it is an issue. > > Thanks and Best Regards, > > Felipe Augusto > > On Tue, Feb 28, 2017 at 9:43 AM, Felipe Augusto Pereira de Figueiredo > <zz4fap@gmail.com> wrote: > > Dear Jonathon, > > > > I tried what you told me. First, I ran setupenv.sh and then executed > > make X310_RFNOC_HG. > > > > The bistream was successfully generated as you can see by the messages > below. > > > > Creating bitstream... > > Writing bitstream > > /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build- > X310_RFNOC_HG/x300.bit... > > INFO: [Vivado 12-1842] Bitgen Completed Successfully. > > > > And again, it has the same size, 15878034, as the other bitstream I > > generated with 2xDDCs, 2xDUCs and 1xFFT. > > > > -rw-rw-r-- 1 zz4fap zz4fap 15878034 Feb 27 22:47 x300.bit > > > > Could you, please, check why this difference exists? I mean, the > > difference of 2 bytes between bitstreams. > > > > While cheking the Makefile at src/uhd-fpga/usrp3/top/x300 I read what > > I think could be a clue to the problem: > > > > ## build/usrp_<product>_fpga_<image_type>.bit: Configuration > > bitstream with header > > ## build/usrp_<product>_fpga_<image_type>.bin: Configuration > > bitstream without header > > > > May the 2 bytes longer bitstream (.bit) contains a 2 bytes long header. > > > > Thanks and Best Regards, > > > > Felipe > > > > On Mon, Feb 27, 2017 at 9:07 PM, Jonathon Pendlum > > <jonathon.pendlum@ettus.com> wrote: > >> Hi Felipe, > >> > >> Make sure to run 'source setupenv.sh' first before make X310_RFNOC_HG > >> > >> On Mon, Feb 27, 2017 at 1:31 PM, Felipe Augusto Pereira de Figueiredo > >> <zz4fap@gmail.com> wrote: > >>> > >>> Hi Jonathon, > >>> > >>> Tried what you said but it didn't work. Could you please be a little > >>> bit more specific about the command I should run. I got some error > >>> regarding the syntax of the command you told me to run. > >>> See output below. > >>> > >>> Thanks and Best Regards, > >>> > >>> Felipe > >>> > >>> > >>> ------------------------------------------------------------ > ------------------------------------------------------------ > --------------------------------- > >>> zz4fap@imecdesktop:~/rfnoc/src/uhd-fpga/usrp3/top/x300$ make > X310_RFNOC_HG > >>> make -f Makefile.x300.inc bin NAME=X310_RFNOC_HG ARCH= PART_ID= > >>> BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 > >>> EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 > >>> X310=1" > >>> find: > >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ > addsub_hls/solution/impl/verilog/': > >>> No such file or directory > >>> make[1]: Entering directory > >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' > >>> BUILDER: Checking tools... > >>> * GNU bash, version 4.3.11(1)-release (x86_64-pc-linux-gnu) > >>> * Python 2.7.6 > >>> * Vivado v2015.4.2 (64-bit) > >>> ======================================================== > >>> BUILDER: Building IP ten_gig_eth_pcs_pma > >>> ======================================================== > >>> BUILDER: Staging IP in build directory... > >>> BUILDER: Reserving IP location: > >>> > >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ > ten_gig_eth_pcs_pma > >>> BUILDER: Retargeting IP to part /... > >>> ERROR: Invalid target format. Must be > >>> <arch>/<device>/<package>/<speedgrade> > >>> BUILDER: Building IP... > >>> > >>> ****** Vivado v2015.4.2 (64-bit) > >>> **** SW Build 1494164 on Fri Feb 26 04:18:54 MST 2016 > >>> **** IP Build 1491208 on Wed Feb 24 03:25:39 MST 2016 > >>> ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. > >>> > >>> source > >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_ > generate_ip.tcl > >>> # set xci_file $::env(XCI_FILE) ; > >>> # set part_name $::env(PART_NAME) ; > >>> # set gen_example_proj $::env(GEN_EXAMPLE) ; > >>> # set synth_ip $::env(SYNTH_IP) ; > >>> # set ip_name [file rootname [file tail $xci_file]] ; > >>> # file delete -force "$xci_file.out" > >>> # create_project -part $part_name -in_memory -ip > >>> WARNING: [#UNDEF] No parts matched '' > >>> ERROR: [Coretcl 2-106] Specified part could not be found. > >>> INFO: [Common 17-206] Exiting Vivado at Mon Feb 27 20:26:39 2017... > >>> BUILDER: Releasing IP location: > >>> > >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ > ten_gig_eth_pcs_pma > >>> make[1]: *** > >>> [/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ > ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] > >>> Error 1 > >>> make[1]: Leaving directory > >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' > >>> make: *** [X310_RFNOC_HG] Error 2 > >>> > >>> ------------------------------------------------------------ > ------------------------------------------------------------ > --------------------------------- > >>> > >>> On Mon, Feb 27, 2017 at 7:55 PM, Jonathon Pendlum > >>> <jonathon.pendlum@ettus.com> wrote: > >>> > Hi Felipe, > >>> > > >>> > What if you build the same image by running make X310_RFNOC_HG in > >>> > usrp3/top/x300? Is it still too large? > >>> > > >>> > On Mon, Feb 27, 2017 at 4:23 AM, Felipe Augusto Pereira de Figueiredo > >>> > via > >>> > USRP-users <usrp-users@lists.ettus.com> wrote: > >>> >> > >>> >> Dear Sam, > >>> >> > >>> >> Many thanks for your tip, I've followed that and it worked. Just > >>> >> changed the size of the macro with the expected bitstream size. > >>> >> > >>> >> I hope someone from Ettus can explain why that problem happens and > if > >>> >> it can be solved other way instead of tweaking the source code. > >>> >> > >>> >> Now the output of "uhd_usrp_probe" is like I had expected it to be. > >>> >> > >>> >> | | _____________________________________________________ > >>> >> | | / > >>> >> | | | RFNoC blocks on this device: > >>> >> | | | > >>> >> | | | * DmaFIFO_0 > >>> >> | | | * Radio_0 > >>> >> | | | * Radio_1 > >>> >> | | | * DDC_0 > >>> >> | | | * DDC_1 > >>> >> | | | * DUC_0 > >>> >> | | | * DUC_1 > >>> >> | | | * FFT_0 > >>> >> > >>> >> Thanks and Best Regards, > >>> >> > >>> >> Felipe > >>> >> > >>> >> On Fri, Feb 24, 2017 at 3:27 PM, Sam Carey <sam@samcarey.com> > wrote: > >>> >> > Howdy, > >>> >> > > >>> >> > I had this problem a while back. My workaround was to simply edit > the > >>> >> > image > >>> >> > loader code so that it is OK with the larger file size. > >>> >> > Just do a search for the smaller byte number in the uhd/host > source > >>> >> > code, > >>> >> > change it to the larger byte number, and rebuild/reinstall uhd. > >>> >> > Apparently, the byte count is not a strict requirement for image > >>> >> > loading. > >>> >> > > >>> >> > You're the second other person I've seen with this problem. > >>> >> > Maybe somebody could apply this change to the main branch or > >>> >> > something? > >>> >> > > >>> >> > -Sam > >>> >> > > >>> >> > > >>> >> > >>> >> _______________________________________________ > >>> >> USRP-users mailing list > >>> >> USRP-users@lists.ettus.com > >>> >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >>> > > >>> > > >> > >> >

Fwiw, I have run into this issue occasionally as well. The fix is to hack the image loader. -Juan On Thu, Mar 2, 2017 at 4:58 PM, Jonathon Pendlum via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi Felipe, > > I do not currently have an explanation why the Xilinx tools generate a > bitstream with a different file size. When I run your build command, the > output bitstream size is 15878032. What OS / Xilinx tools are you building > with? > > > > Jonathon > > On Thu, Mar 2, 2017 at 11:07 AM, Felipe Augusto Pereira de Figueiredo < > zz4fap@gmail.com> wrote: > >> Dear Jonathon, >> >> Do you have any update on the 2 bytes larger bitstream issue? >> >> I was expecting someone from ettus to give us an explanation on that >> and if it is an issue. >> >> Thanks and Best Regards, >> >> Felipe Augusto >> >> On Tue, Feb 28, 2017 at 9:43 AM, Felipe Augusto Pereira de Figueiredo >> <zz4fap@gmail.com> wrote: >> > Dear Jonathon, >> > >> > I tried what you told me. First, I ran setupenv.sh and then executed >> > make X310_RFNOC_HG. >> > >> > The bistream was successfully generated as you can see by the messages >> below. >> > >> > Creating bitstream... >> > Writing bitstream >> > /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_ >> RFNOC_HG/x300.bit... >> > INFO: [Vivado 12-1842] Bitgen Completed Successfully. >> > >> > And again, it has the same size, 15878034, as the other bitstream I >> > generated with 2xDDCs, 2xDUCs and 1xFFT. >> > >> > -rw-rw-r-- 1 zz4fap zz4fap 15878034 Feb 27 22:47 x300.bit >> > >> > Could you, please, check why this difference exists? I mean, the >> > difference of 2 bytes between bitstreams. >> > >> > While cheking the Makefile at src/uhd-fpga/usrp3/top/x300 I read what >> > I think could be a clue to the problem: >> > >> > ## build/usrp_<product>_fpga_<image_type>.bit: Configuration >> > bitstream with header >> > ## build/usrp_<product>_fpga_<image_type>.bin: Configuration >> > bitstream without header >> > >> > May the 2 bytes longer bitstream (.bit) contains a 2 bytes long header. >> > >> > Thanks and Best Regards, >> > >> > Felipe >> > >> > On Mon, Feb 27, 2017 at 9:07 PM, Jonathon Pendlum >> > <jonathon.pendlum@ettus.com> wrote: >> >> Hi Felipe, >> >> >> >> Make sure to run 'source setupenv.sh' first before make X310_RFNOC_HG >> >> >> >> On Mon, Feb 27, 2017 at 1:31 PM, Felipe Augusto Pereira de Figueiredo >> >> <zz4fap@gmail.com> wrote: >> >>> >> >>> Hi Jonathon, >> >>> >> >>> Tried what you said but it didn't work. Could you please be a little >> >>> bit more specific about the command I should run. I got some error >> >>> regarding the syntax of the command you told me to run. >> >>> See output below. >> >>> >> >>> Thanks and Best Regards, >> >>> >> >>> Felipe >> >>> >> >>> >> >>> ------------------------------------------------------------ >> ------------------------------------------------------------ >> --------------------------------- >> >>> zz4fap@imecdesktop:~/rfnoc/src/uhd-fpga/usrp3/top/x300$ make >> X310_RFNOC_HG >> >>> make -f Makefile.x300.inc bin NAME=X310_RFNOC_HG ARCH= PART_ID= >> >>> BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 >> >>> EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 >> >>> X310=1" >> >>> find: >> >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/add >> sub_hls/solution/impl/verilog/': >> >>> No such file or directory >> >>> make[1]: Entering directory >> >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' >> >>> BUILDER: Checking tools... >> >>> * GNU bash, version 4.3.11(1)-release (x86_64-pc-linux-gnu) >> >>> * Python 2.7.6 >> >>> * Vivado v2015.4.2 (64-bit) >> >>> ======================================================== >> >>> BUILDER: Building IP ten_gig_eth_pcs_pma >> >>> ======================================================== >> >>> BUILDER: Staging IP in build directory... >> >>> BUILDER: Reserving IP location: >> >>> >> >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_ >> gig_eth_pcs_pma >> >>> BUILDER: Retargeting IP to part /... >> >>> ERROR: Invalid target format. Must be >> >>> <arch>/<device>/<package>/<speedgrade> >> >>> BUILDER: Building IP... >> >>> >> >>> ****** Vivado v2015.4.2 (64-bit) >> >>> **** SW Build 1494164 on Fri Feb 26 04:18:54 MST 2016 >> >>> **** IP Build 1491208 on Wed Feb 24 03:25:39 MST 2016 >> >>> ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. >> >>> >> >>> source >> >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_gene >> rate_ip.tcl >> >>> # set xci_file $::env(XCI_FILE) ; >> >>> # set part_name $::env(PART_NAME) ; >> >>> # set gen_example_proj $::env(GEN_EXAMPLE) ; >> >>> # set synth_ip $::env(SYNTH_IP) ; >> >>> # set ip_name [file rootname [file tail $xci_file]] ; >> >>> # file delete -force "$xci_file.out" >> >>> # create_project -part $part_name -in_memory -ip >> >>> WARNING: [#UNDEF] No parts matched '' >> >>> ERROR: [Coretcl 2-106] Specified part could not be found. >> >>> INFO: [Common 17-206] Exiting Vivado at Mon Feb 27 20:26:39 2017... >> >>> BUILDER: Releasing IP location: >> >>> >> >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_ >> gig_eth_pcs_pma >> >>> make[1]: *** >> >>> [/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten >> _gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] >> >>> Error 1 >> >>> make[1]: Leaving directory >> >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' >> >>> make: *** [X310_RFNOC_HG] Error 2 >> >>> >> >>> ------------------------------------------------------------ >> ------------------------------------------------------------ >> --------------------------------- >> >>> >> >>> On Mon, Feb 27, 2017 at 7:55 PM, Jonathon Pendlum >> >>> <jonathon.pendlum@ettus.com> wrote: >> >>> > Hi Felipe, >> >>> > >> >>> > What if you build the same image by running make X310_RFNOC_HG in >> >>> > usrp3/top/x300? Is it still too large? >> >>> > >> >>> > On Mon, Feb 27, 2017 at 4:23 AM, Felipe Augusto Pereira de >> Figueiredo >> >>> > via >> >>> > USRP-users <usrp-users@lists.ettus.com> wrote: >> >>> >> >> >>> >> Dear Sam, >> >>> >> >> >>> >> Many thanks for your tip, I've followed that and it worked. Just >> >>> >> changed the size of the macro with the expected bitstream size. >> >>> >> >> >>> >> I hope someone from Ettus can explain why that problem happens and >> if >> >>> >> it can be solved other way instead of tweaking the source code. >> >>> >> >> >>> >> Now the output of "uhd_usrp_probe" is like I had expected it to be. >> >>> >> >> >>> >> | | _____________________________________________________ >> >>> >> | | / >> >>> >> | | | RFNoC blocks on this device: >> >>> >> | | | >> >>> >> | | | * DmaFIFO_0 >> >>> >> | | | * Radio_0 >> >>> >> | | | * Radio_1 >> >>> >> | | | * DDC_0 >> >>> >> | | | * DDC_1 >> >>> >> | | | * DUC_0 >> >>> >> | | | * DUC_1 >> >>> >> | | | * FFT_0 >> >>> >> >> >>> >> Thanks and Best Regards, >> >>> >> >> >>> >> Felipe >> >>> >> >> >>> >> On Fri, Feb 24, 2017 at 3:27 PM, Sam Carey <sam@samcarey.com> >> wrote: >> >>> >> > Howdy, >> >>> >> > >> >>> >> > I had this problem a while back. My workaround was to simply >> edit the >> >>> >> > image >> >>> >> > loader code so that it is OK with the larger file size. >> >>> >> > Just do a search for the smaller byte number in the uhd/host >> source >> >>> >> > code, >> >>> >> > change it to the larger byte number, and rebuild/reinstall uhd. >> >>> >> > Apparently, the byte count is not a strict requirement for image >> >>> >> > loading. >> >>> >> > >> >>> >> > You're the second other person I've seen with this problem. >> >>> >> > Maybe somebody could apply this change to the main branch or >> >>> >> > something? >> >>> >> > >> >>> >> > -Sam >> >>> >> > >> >>> >> > >> >>> >> >> >>> >> _______________________________________________ >> >>> >> USRP-users mailing list >> >>> >> USRP-users@lists.ettus.com >> >>> >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >>> > >> >>> > >> >> >> >> >> > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

Hey guys, Yes, I tweaked the image loader script and it worked. I just wanted to understand it better. @Jonathon I'm using Ubuntu 14.04.5 and Vivado 2015.4.2. Thanks and Best Regards, Felipe On Thu, Mar 2, 2017 at 11:42 PM, Juan Francisco <jfrancisco1527@gmail.com> wrote: > Fwiw, I have run into this issue occasionally as well. The fix is to hack > the image loader. > > -Juan > > On Thu, Mar 2, 2017 at 4:58 PM, Jonathon Pendlum via USRP-users > <usrp-users@lists.ettus.com> wrote: >> >> Hi Felipe, >> >> I do not currently have an explanation why the Xilinx tools generate a >> bitstream with a different file size. When I run your build command, the >> output bitstream size is 15878032. What OS / Xilinx tools are you building >> with? >> >> >> >> Jonathon >> >> On Thu, Mar 2, 2017 at 11:07 AM, Felipe Augusto Pereira de Figueiredo >> <zz4fap@gmail.com> wrote: >>> >>> Dear Jonathon, >>> >>> Do you have any update on the 2 bytes larger bitstream issue? >>> >>> I was expecting someone from ettus to give us an explanation on that >>> and if it is an issue. >>> >>> Thanks and Best Regards, >>> >>> Felipe Augusto >>> >>> On Tue, Feb 28, 2017 at 9:43 AM, Felipe Augusto Pereira de Figueiredo >>> <zz4fap@gmail.com> wrote: >>> > Dear Jonathon, >>> > >>> > I tried what you told me. First, I ran setupenv.sh and then executed >>> > make X310_RFNOC_HG. >>> > >>> > The bistream was successfully generated as you can see by the messages >>> > below. >>> > >>> > Creating bitstream... >>> > Writing bitstream >>> > >>> > /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-X310_RFNOC_HG/x300.bit... >>> > INFO: [Vivado 12-1842] Bitgen Completed Successfully. >>> > >>> > And again, it has the same size, 15878034, as the other bitstream I >>> > generated with 2xDDCs, 2xDUCs and 1xFFT. >>> > >>> > -rw-rw-r-- 1 zz4fap zz4fap 15878034 Feb 27 22:47 x300.bit >>> > >>> > Could you, please, check why this difference exists? I mean, the >>> > difference of 2 bytes between bitstreams. >>> > >>> > While cheking the Makefile at src/uhd-fpga/usrp3/top/x300 I read what >>> > I think could be a clue to the problem: >>> > >>> > ## build/usrp_<product>_fpga_<image_type>.bit: Configuration >>> > bitstream with header >>> > ## build/usrp_<product>_fpga_<image_type>.bin: Configuration >>> > bitstream without header >>> > >>> > May the 2 bytes longer bitstream (.bit) contains a 2 bytes long header. >>> > >>> > Thanks and Best Regards, >>> > >>> > Felipe >>> > >>> > On Mon, Feb 27, 2017 at 9:07 PM, Jonathon Pendlum >>> > <jonathon.pendlum@ettus.com> wrote: >>> >> Hi Felipe, >>> >> >>> >> Make sure to run 'source setupenv.sh' first before make X310_RFNOC_HG >>> >> >>> >> On Mon, Feb 27, 2017 at 1:31 PM, Felipe Augusto Pereira de Figueiredo >>> >> <zz4fap@gmail.com> wrote: >>> >>> >>> >>> Hi Jonathon, >>> >>> >>> >>> Tried what you said but it didn't work. Could you please be a little >>> >>> bit more specific about the command I should run. I got some error >>> >>> regarding the syntax of the command you told me to run. >>> >>> See output below. >>> >>> >>> >>> Thanks and Best Regards, >>> >>> >>> >>> Felipe >>> >>> >>> >>> >>> >>> >>> >>> --------------------------------------------------------------------------------------------------------------------------------------------------------- >>> >>> zz4fap@imecdesktop:~/rfnoc/src/uhd-fpga/usrp3/top/x300$ make >>> >>> X310_RFNOC_HG >>> >>> make -f Makefile.x300.inc bin NAME=X310_RFNOC_HG ARCH= PART_ID= >>> >>> BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 X310=1 >>> >>> EXTRA_DEFS="BUILD_1G=1 BUILD_10G=1 SFP0_1GBE=1 SFP1_10GBE=1 RFNOC=1 >>> >>> X310=1" >>> >>> find: >>> >>> >>> >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/addsub_hls/solution/impl/verilog/': >>> >>> No such file or directory >>> >>> make[1]: Entering directory >>> >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' >>> >>> BUILDER: Checking tools... >>> >>> * GNU bash, version 4.3.11(1)-release (x86_64-pc-linux-gnu) >>> >>> * Python 2.7.6 >>> >>> * Vivado v2015.4.2 (64-bit) >>> >>> ======================================================== >>> >>> BUILDER: Building IP ten_gig_eth_pcs_pma >>> >>> ======================================================== >>> >>> BUILDER: Staging IP in build directory... >>> >>> BUILDER: Reserving IP location: >>> >>> >>> >>> >>> >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_gig_eth_pcs_pma >>> >>> BUILDER: Retargeting IP to part /... >>> >>> ERROR: Invalid target format. Must be >>> >>> <arch>/<device>/<package>/<speedgrade> >>> >>> BUILDER: Building IP... >>> >>> >>> >>> ****** Vivado v2015.4.2 (64-bit) >>> >>> **** SW Build 1494164 on Fri Feb 26 04:18:54 MST 2016 >>> >>> **** IP Build 1491208 on Wed Feb 24 03:25:39 MST 2016 >>> >>> ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. >>> >>> >>> >>> source >>> >>> >>> >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_generate_ip.tcl >>> >>> # set xci_file $::env(XCI_FILE) ; >>> >>> # set part_name $::env(PART_NAME) ; >>> >>> # set gen_example_proj $::env(GEN_EXAMPLE) ; >>> >>> # set synth_ip $::env(SYNTH_IP) ; >>> >>> # set ip_name [file rootname [file tail $xci_file]] ; >>> >>> # file delete -force "$xci_file.out" >>> >>> # create_project -part $part_name -in_memory -ip >>> >>> WARNING: [#UNDEF] No parts matched '' >>> >>> ERROR: [Coretcl 2-106] Specified part could not be found. >>> >>> INFO: [Common 17-206] Exiting Vivado at Mon Feb 27 20:26:39 2017... >>> >>> BUILDER: Releasing IP location: >>> >>> >>> >>> >>> >>> /home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_gig_eth_pcs_pma >>> >>> make[1]: *** >>> >>> >>> >>> [/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] >>> >>> Error 1 >>> >>> make[1]: Leaving directory >>> >>> `/home/zz4fap/rfnoc/src/uhd-fpga/usrp3/top/x300' >>> >>> make: *** [X310_RFNOC_HG] Error 2 >>> >>> >>> >>> >>> >>> --------------------------------------------------------------------------------------------------------------------------------------------------------- >>> >>> >>> >>> On Mon, Feb 27, 2017 at 7:55 PM, Jonathon Pendlum >>> >>> <jonathon.pendlum@ettus.com> wrote: >>> >>> > Hi Felipe, >>> >>> > >>> >>> > What if you build the same image by running make X310_RFNOC_HG in >>> >>> > usrp3/top/x300? Is it still too large? >>> >>> > >>> >>> > On Mon, Feb 27, 2017 at 4:23 AM, Felipe Augusto Pereira de >>> >>> > Figueiredo >>> >>> > via >>> >>> > USRP-users <usrp-users@lists.ettus.com> wrote: >>> >>> >> >>> >>> >> Dear Sam, >>> >>> >> >>> >>> >> Many thanks for your tip, I've followed that and it worked. Just >>> >>> >> changed the size of the macro with the expected bitstream size. >>> >>> >> >>> >>> >> I hope someone from Ettus can explain why that problem happens and >>> >>> >> if >>> >>> >> it can be solved other way instead of tweaking the source code. >>> >>> >> >>> >>> >> Now the output of "uhd_usrp_probe" is like I had expected it to >>> >>> >> be. >>> >>> >> >>> >>> >> | | _____________________________________________________ >>> >>> >> | | / >>> >>> >> | | | RFNoC blocks on this device: >>> >>> >> | | | >>> >>> >> | | | * DmaFIFO_0 >>> >>> >> | | | * Radio_0 >>> >>> >> | | | * Radio_1 >>> >>> >> | | | * DDC_0 >>> >>> >> | | | * DDC_1 >>> >>> >> | | | * DUC_0 >>> >>> >> | | | * DUC_1 >>> >>> >> | | | * FFT_0 >>> >>> >> >>> >>> >> Thanks and Best Regards, >>> >>> >> >>> >>> >> Felipe >>> >>> >> >>> >>> >> On Fri, Feb 24, 2017 at 3:27 PM, Sam Carey <sam@samcarey.com> >>> >>> >> wrote: >>> >>> >> > Howdy, >>> >>> >> > >>> >>> >> > I had this problem a while back. My workaround was to simply >>> >>> >> > edit the >>> >>> >> > image >>> >>> >> > loader code so that it is OK with the larger file size. >>> >>> >> > Just do a search for the smaller byte number in the uhd/host >>> >>> >> > source >>> >>> >> > code, >>> >>> >> > change it to the larger byte number, and rebuild/reinstall uhd. >>> >>> >> > Apparently, the byte count is not a strict requirement for image >>> >>> >> > loading. >>> >>> >> > >>> >>> >> > You're the second other person I've seen with this problem. >>> >>> >> > Maybe somebody could apply this change to the main branch or >>> >>> >> > something? >>> >>> >> > >>> >>> >> > -Sam >>> >>> >> > >>> >>> >> > >>> >>> >> >>> >>> >> _______________________________________________ >>> >>> >> USRP-users mailing list >>> >>> >> USRP-users@lists.ettus.com >>> >>> >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> > >>> >>> > >>> >> >>> >> >> >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >