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List: discuss@lists.openscad.org
From: Jordan Brown
Re: Bug in my code or OpenSCAD?
Thu, Oct 31, 2024 4:57 AM
But a rotate_extrude of a triangle with one side on the Y axis produces
a cone, and if you put the top point of the triangle at [0,0] then
you'll get the same effect I wanted - scaling it up leaves the top part
all the same.
List: discuss@lists.openscad.org
From: larry
Re: Hole with radius
Sat, Jun 7, 2025 5:41 PM
> >
> > include
> > size = 20;
> > $fa=1;$fs=.3;
> > diff()
> > cuboid(size)
> > attach(TOP,TOP,inside=true)
> > cyl(h=size,d=4,rounding=-2,extra=1); // extra adds length to
> > avoid z-fighting
> >
> >
> > image.png
> >
> >
> > On Fri, Jun 6, 2025 at 4:33 PM Joe Weinpert via Discuss
> > wrote
List: usrp-users@lists.ettus.com
From: perper@o2.pl
Re: X440 Rebuilding boot.bin
Tue, Sep 23, 2025 3:15 AM
perper@o2.pl wrote:
> https://github.com/EttusResearch/uhd/blob/07a7a92ad6e09cc7e84aae5990aff563a4546e83/fpga/usrp3/top/x400/build_x4xx.tcl#L11tovivado_utils::initialize_project 1Then in uhd/pga/usrp3/top/x400/ do:source setupenv.shmakeAfter this ends you should have an \*.xpr file in one of build directories. You can open this file Vivado.
List: usrp-users@lists.ettus.com
From: ri28856@mit.edu
Building x310 FPGA image for UHD 4.3.0
Fri, Dec 23, 2022 4:52 PM
: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: \[IP_Flow 19-
List: usrp-users@lists.ettus.com
From: ri28856@mit.edu
Re: Building x310 FPGA image for UHD 4.3.0
Tue, Jan 3, 2023 8:39 PM
/Makefile.inc:20: LIB_IP_AXI_HB31_TRGT] Error 1`
`make[1]: Leaving directory '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300'`
List: usrp-users@lists.ettus.com
From: perper@o2.pl
Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Sun, Jan 29, 2023 8:13 PM
to generate target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci`
>
> `[00:00:05] Current task: Initialization +++ Current Phase: Finished`
>
> `[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part xc7z100ffg900-2 -mode out_of_context`
>
> `[00:00:05] Starting Synthesis Command`
List: usrp-users@lists.ettus.com
From: jmaloyan@umass.edu
Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Fri, Jan 27, 2023 10:17 PM
Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'`
`make: *** [Makefile:90: N3X0_IP] Error 2`
List: usrp-users@lists.ettus.com
From: Justin Tallon .
Re: [USRP-users] b210 fpga source makefile trouble
Wed, Jul 15, 2015 6:00 PM
usrp3/top/b200/build-B210/b200.xise
>>>
>>> Project Generation DONE ...
List: hbcu-lib@lists.hbculibraries.org
From: Sandra Phoenix
Southern lists five finalists for chancellor
Thu, Apr 7, 2011 12:25 PM
Anderson, Llorens and Jennings have been considered for top Southern jobs in the past.
The search committee voted 12-2 to invite the top five scorers.
List: trawlers@lists.trawlering.com
From: JHWardJr@aol.com
enclosure
Tue, May 3, 2011 9:43 PM
My full enclosure top on my Present 42 (seems to be pretty standard design
as others look the same - factory?) is in too good a condition to replace,
but not too pretty anymore. Made of vinyl on top and sides are vinyl, as
well (white). Spent it's life in FL, so the winter stiffness I endure in
NC was not as much of an issue there.