Are there any instructions or guidance on how to rebuild the boot.bin including the FSBL? I want to enable the M_AXI_HPM1_FPD bus in the PS block design so I believe I need to rebuild the FSBL and add it to the boot.bin. Any insight would be appreciated. Thanks, Brian

Hello Brian, I had to go through this topic thoroughly when I did port of X410 code to ZCU111. It was over two years ago but I still remember something. X410 and X440 don’t use FSBL code from Xilinx to boot RFSoC like in autogenerated Petalinux projects. They took some files from hardware exported in Vivado for the project (File->Export->Export Hardware - it generates a zip file) and put them into SPL (Secondary Program Loader) which is u-boot’s replacement for FSBL. In the exported hardware there is file psu_init_gpl.c. The configuration that you need to set is most probably stored in it.This file + pm_cfg_obj.c (I’ll describe generation of this file later) are added to u-boot by this patch:https://github.com/EttusResearch/meta-ettus/blob/kirkstone/meta-ettus-bsp/recipes-bsp/u-boot/files/ni-titanium/0006-board-ni-add-support-for-X410.patch There’s one pair of such files for each X410’s revision but I don’t see any for X440. Maybe they share them between X410 and X440. Now I don’t have the exact guide how to do the export. Only what I remember, so there might be something wrong/missing.I did it by generating a project that can be normally opened and modified in Vivado.To generate the project I modified this line: https://github.com/EttusResearch/uhd/blob/07a7a92ad6e09cc7e84aae5990aff563a4546e83/fpga/usrp3/top/x400/build_x4xx.tcl#L11tovivado_utils::initialize_project 1Then in uhd/pga/usrp3/top/x400/ do:source setupenv.shmakeAfter this ends you should have an \*.xpr file in one of build directories. You can open this file Vivado. Then find x4xx_ps_rfdc_bd block diagram, open it and edit ZYNQ configuration to enable the bus that you need. After that I don’t remember if you have to do synthesis or you can straight away go to File->Export->Export Hardware and create a zip file with psu_init_gpl.c and a header (psu_init_gpl.h ?). From this file you generate a pm_cfg_obj.c file with use of this tool: https://github.com/u-boot/u-boot/blob/master/tools/zynqmp_psu_init_minimize.sh The usage is in the source code of this script (this particular step was figured out by Emil J Tywoniak, so credit goes to him here): zynqmp_psu_init_minimize.sh /path/to/original/psu_init_gpl_c_and_h/ outdir Last time I used this script (over 2 years ago) it was failing on some #ifdef boilerplate from the psu_init_gpl.c file. So I had to remove that part for the generation to pass. Then you need to take the generated files (pm_cfg_obj.c, psu_init_gpl.c), compare them with the files from the 0006-board-ni-add-support-for-X410.patch and either edit this patch or create a new one with you changes only. Forgive me, but I don't remember easiest way to do that with yocto. One way is to build yocto image for X440 with use of kas, find u-boot source code in the build directory, change the files there and create a patch with use of git. Then add the path to the patch here: https://github.com/EttusResearch/meta-ettus/blob/1c00f1ce66d4d141f0be6565fbd562d8692777d2/meta-ettus-bsp/recipes-bsp/u-boot/u-boot_2020.10_ni.inc#L13 Then build the whole yocto image (or just u-boot if you know how) for X410/X440 and flash it on an SD-CARD I hope there is a simpler way to do what you want, but I don't know any. Best Regards,\ Piotr Krysik

perper@o2.pl wrote: > https://github.com/EttusResearch/uhd/blob/07a7a92ad6e09cc7e84aae5990aff563a4546e83/fpga/usrp3/top/x400/build_x4xx.tcl#L11tovivado_utils::initialize_project 1Then in uhd/pga/usrp3/top/x400/ do:source setupenv.shmakeAfter this ends you should have an \*.xpr file in one of build directories. You can open this file Vivado. Then find x4xx_ps_rfdc_bd block diagram, open it and edit ZYNQ configuration to enable the bus that you need. After that I don’t remember if you have to do synthesis or you can straight away go to File->Export->Export Hardware and create a zip file with psu_init_gpl.c and a header (psu_init_gpl.h ?). Something was messed with this paragraph. It was: https://github.com/EttusResearch/uhd/blob/07a7a92ad6e09cc7e84aae5990aff563a4546e83/fpga/usrp3/top/x400/build_x4xx.tcl#L11 to vivado_utils::initialize_project 1 Then in uhd/pga/usrp3/top/x400/ do: source setupenv.sh\ make After this ends you should have an \*.xpr file in one of build directories. You can open this file Vivado. Then find x4xx_ps_rfdc_bd block diagram, open it and edit ZYNQ configuration to enable the bus that you need. After that I don’t remember if you have to do synthesis or you can straight away go to File->Export->Export Hardware and create a zip file with psu_init_gpl.c and a header (psu_init_gpl.h ?). … Piotr Krysik