usrp-users@lists.ettus.com
Discussion and technical support related to USRP, UHD, RFNoC
View all threadsError when synthesizing example OOT block : IP "cmplx_mul" is locked
Hello,
I have run into an issue when trying to synthesize the “gain” RFNoC as described in the tutorial here https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the verilog file “rfnoc_block_gain.v”, the module is instantiated there, but I am unsure how I should proceed working around this.
Here is the output of the vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved
And here is the output of the error
---=======================
BUILDER: Building IP cmplx_mul
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log cmplx_mul.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
make[1]: *** [/rfnoc-foo/fpga//ip/cmplx_mul/Makefile.inc:21: LIB_IP_CMPLX_MUL_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
jmaloyan@umass.edu wrote:
Hello,
I have run into an issue when trying to synthesize the “gain” RFNoC as described in the tutorial here https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the verilog file “rfnoc_block_gain.v”, the module is instantiated there, but I am unsure how I should proceed working around this.
Here is the output of the vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved
And here is the output of the error
---=======================
BUILDER: Building IP cmplx_mul
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log cmplx_mul.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
make[1]: *** [/rfnoc-foo/fpga//ip/cmplx_mul/Makefile.inc:21: LIB_IP_CMPLX_MUL_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
Hello,
There was issue with ‘cmplx_mul‘ configuration not being updated after migration of UHD to Vivado 2021.1 from Vivado 2019.1.
This is the case for UHD-4.3 release and the issue was fixed in master branch.
For more details look here: https://github.com/EttusResearch/uhd/issues/635
Best Regards,
Piotr Krysik
Same here.
Since switching to Vivado 2021.1 and UHD-4.3 even compiling the stock firmware results in [IP_Flow 19-2162] IP 'axi_hb31' is locked.
Apparently, this error is well known https://support.xilinx.com/s/article/58832?language=en_US
I'm trying to switch to UHD 4.4 to see if this error goes away. Everything was working really well in UHD-4.2 and Vivado 2019.1.
Best,
Lorenzo
From: jmaloyan@umass.edu jmaloyan@umass.edu
Sent: Friday, January 27, 2023 2:17 PM
To: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: [USRP-users] Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Hello,
I have run into an issue when trying to synthesize the “gain” RFNoC as described in the tutorial here https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the verilog file “rfnoc_block_gain.v”, the module is instantiated there, but I am unsure how I should proceed working around this.
Here is the output of the vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved
And here is the output of the error
---=======================
BUILDER: Building IP cmplx_mul
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log cmplx_mul.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
make[1]: *** [/rfnoc-foo/fpga//ip/cmplx_mul/Makefile.inc:21: LIB_IP_CMPLX_MUL_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
I tried installing Vivado 2021.1 and applying the right patch, using UHD-4.4 I still get the following error message:
---=======================
BUILDER: Building IP axi_hb31
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31
BUILDER: Retargeting IP to part kintex7/xc7k325t/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /home/lorenzo/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log axi_hb31.log -nojournal
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
[00:00:04] Current task: Initialization +++ Current Phase: Starting
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
[00:00:04] Current task: Initialization +++ Current Phase: Finished
[00:00:04] Executing Tcl: synth_design -top axi_hb31 -part xc7k325tffg900-2 -mode out_of_context
[00:00:04] Starting Synthesis Command
[00:00:04] Current task: Synthesis +++ Current Phase: Starting
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
Currently looking for a workaround before reverting to 2019.1 and UHD 4.2
Lorenzo
From: Minutolo, Lorenzo minutolo@caltech.edu
Sent: Tuesday, January 31, 2023 11:48 AM
To: jmaloyan@umass.edu jmaloyan@umass.edu; usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: [USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Same here.
Since switching to Vivado 2021.1 and UHD-4.3 even compiling the stock firmware results in [IP_Flow 19-2162] IP 'axi_hb31' is locked.
Apparently, this error is well known https://support.xilinx.com/s/article/58832?language=en_US
I'm trying to switch to UHD 4.4 to see if this error goes away. Everything was working really well in UHD-4.2 and Vivado 2019.1.
Best,
Lorenzo
From: jmaloyan@umass.edu jmaloyan@umass.edu
Sent: Friday, January 27, 2023 2:17 PM
To: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: [USRP-users] Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Hello,
I have run into an issue when trying to synthesize the “gain” RFNoC as described in the tutorial here https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the verilog file “rfnoc_block_gain.v”, the module is instantiated there, but I am unsure how I should proceed working around this.
Here is the output of the vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved
And here is the output of the error
---=======================
BUILDER: Building IP cmplx_mul
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log cmplx_mul.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
make[1]: *** [/rfnoc-foo/fpga//ip/cmplx_mul/Makefile.inc:21: LIB_IP_CMPLX_MUL_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
After reading about this conversation on the mailing list https://lists.ettus.com/empathy/thread/DGJBPK6YADKXM2ETKPEVQQ7F5ALJCIDD
I went ahead and erased my UHD distribution folder and started from scratch. Here is how to reproduce what I did:
Given a patched version of Vivado installed on the system:
/tools/Xilinx/Vivado/2021.1/bin/vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
Commands:
git clone git clone https://github.com/EttusResearch/uhd.git
cd uhd
git checkout UHD-4.4
<optional>
cd host
mkdir build && cd build
cmake ..
make -j10
sudo make install
cd ../..
<end optional>
cd fpga/usrp3/top/x300/
rfnoc_image_builder -c -d x300 -y ./x300_rfnoc_image_core.yml -t X300_HG -p /tools/Xilinx/Vivado/
This results in the error reported below.
From: Minutolo, Lorenzo minutolo@caltech.edu
Sent: Tuesday, January 31, 2023 2:20 PM
To: jmaloyan@umass.edu jmaloyan@umass.edu; usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: [USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
I tried installing Vivado 2021.1 and applying the right patch, using UHD-4.4 I still get the following error message:
---=======================
BUILDER: Building IP axi_hb31
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31
BUILDER: Retargeting IP to part kintex7/xc7k325t/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /home/lorenzo/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log axi_hb31.log -nojournal
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
[00:00:04] Current task: Initialization +++ Current Phase: Starting
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
[00:00:04] Current task: Initialization +++ Current Phase: Finished
[00:00:04] Executing Tcl: synth_design -top axi_hb31 -part xc7k325tffg900-2 -mode out_of_context
[00:00:04] Starting Synthesis Command
[00:00:04] Current task: Synthesis +++ Current Phase: Starting
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
Currently looking for a workaround before reverting to 2019.1 and UHD 4.2
Lorenzo
From: Minutolo, Lorenzo minutolo@caltech.edu
Sent: Tuesday, January 31, 2023 11:48 AM
To: jmaloyan@umass.edu jmaloyan@umass.edu; usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: [USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Same here.
Since switching to Vivado 2021.1 and UHD-4.3 even compiling the stock firmware results in [IP_Flow 19-2162] IP 'axi_hb31' is locked.
Apparently, this error is well known https://support.xilinx.com/s/article/58832?language=en_US
I'm trying to switch to UHD 4.4 to see if this error goes away. Everything was working really well in UHD-4.2 and Vivado 2019.1.
Best,
Lorenzo
From: jmaloyan@umass.edu jmaloyan@umass.edu
Sent: Friday, January 27, 2023 2:17 PM
To: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: [USRP-users] Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Hello,
I have run into an issue when trying to synthesize the “gain” RFNoC as described in the tutorial here https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the verilog file “rfnoc_block_gain.v”, the module is instantiated there, but I am unsure how I should proceed working around this.
Here is the output of the vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved
And here is the output of the error
---=======================
BUILDER: Building IP cmplx_mul
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log cmplx_mul.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
make[1]: *** [/rfnoc-foo/fpga//ip/cmplx_mul/Makefile.inc:21: LIB_IP_CMPLX_MUL_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
Hi Lorenzo,
I tried your steps but couldn't reproduce the issue you're seeing. I wonder
if somehow the patch is not being picked up, or perhaps you somehow have
stale build files. Can you run the following?
cd fpga/usrp3/top/x300/
source setupenv.sh
What's the output of setupenv.sh?
At this point you can try:
make cleanall
make X300_HG
Typically the IP locked issue happens when there is a mismatch between the
version of Vivado that was used to generate the IP and the version of
Vivado that is being used to build the FPGA. You can see the Vivado version
that was used to generate the IP here:
https://github.com/EttusResearch/uhd/blob/UHD-4.4/fpga/usrp3/lib/ip/axi_hb31/axi_hb31.xci#L247
You can see the version of the version of Vivado you're using to build the
FPGA when you run "source setupenv.sh". It is also possible to open the IP
in Vivado and unlock it by fixing whatever version mismatch it sees, but
you should be building with 2021.1_AR76780 or else other IP will give you
similar problems.
Please double check that you don't have changes or untracked files in your
repo (running git status should tell you) or old builds laying around
(make cleanall should remove those). And make sure that setupenv.sh
reports v2021.1_AR76780. If you have multiple patches or the same patch
installed in multiple places, that might also cause a version mismatch.
Wade
On Tue, Jan 31, 2023 at 5:06 PM Minutolo, Lorenzo minutolo@caltech.edu
wrote:
After reading about this conversation on the mailing list
https://lists.ettus.com/empathy/thread/DGJBPK6YADKXM2ETKPEVQQ7F5ALJCIDD
I went ahead and erased my UHD distribution folder and started from
scratch. Here is how to reproduce what I did:
Given a patched version of Vivado installed on the system:
/tools/Xilinx/Vivado/2021.1/bin/vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
Commands:
git clone git clone https://github.com/EttusResearch/uhd.git
cd uhd
git checkout UHD-4.4
<optional>
cd host
mkdir build && cd build
cmake ..
make -j10
sudo make install
cd ../..
<end optional>
cd fpga/usrp3/top/x300/
rfnoc_image_builder -c -d x300 -y ./x300_rfnoc_image_core.yml -t X300_HG
-p /tools/Xilinx/Vivado/
This results in the error reported below.
From: Minutolo, Lorenzo minutolo@caltech.edu
Sent: Tuesday, January 31, 2023 2:20 PM
To: jmaloyan@umass.edu jmaloyan@umass.edu; usrp-users@lists.ettus.com
usrp-users@lists.ettus.com
Subject: [USRP-users] Re: Error when synthesizing example OOT block :
IP "cmplx_mul" is locked
I tried installing Vivado 2021.1 and applying the right patch, using
UHD-4.4 I still get the following error message:
---=======================
BUILDER: Building IP axi_hb31
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31
BUILDER: Retargeting IP to part kintex7/xc7k325t/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source
/home/lorenzo/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log
axi_hb31.log -nojournal
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
[00:00:04] Current task: Initialization +++ Current Phase: Starting
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the
following file is locked:
/home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the
following file is locked:
/home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
[00:00:04] Current task: Initialization +++ Current Phase: Finished
[00:00:04] Executing Tcl: synth_design -top axi_hb31 -part
xc7k325tffg900-2 -mode out_of_context
[00:00:04] Starting Synthesis Command
[00:00:04] Current task: Synthesis +++ Current Phase: Starting
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products
for Synthesis target. These output products could be required for
synthesis, please generate the output products using the generate_target or
synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources
specified
Currently looking for a workaround before reverting to 2019.1 and UHD 4.2
Lorenzo
From: Minutolo, Lorenzo minutolo@caltech.edu
Sent: Tuesday, January 31, 2023 11:48 AM
To: jmaloyan@umass.edu jmaloyan@umass.edu; usrp-users@lists.ettus.com
usrp-users@lists.ettus.com
Subject: [USRP-users] Re: Error when synthesizing example OOT block :
IP "cmplx_mul" is locked
Same here.
Since switching to Vivado 2021.1 and UHD-4.3 even compiling the stock
firmware results in [IP_Flow 19-2162] IP 'axi_hb31' is locked.
Apparently, this error is well known
https://support.xilinx.com/s/article/58832?language=en_US
I'm trying to switch to UHD 4.4 to see if this error goes away. Everything
was working really well in UHD-4.2 and Vivado 2019.1.
Best,
Lorenzo
From: jmaloyan@umass.edu jmaloyan@umass.edu
Sent: Friday, January 27, 2023 2:17 PM
To: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: [USRP-users] Error when synthesizing example OOT block : IP
"cmplx_mul" is locked
Hello,
I have run into an issue when trying to synthesize the “gain” RFNoC as
described in the tutorial here
https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the
verilog file “rfnoc_block_gain.v”, the module is instantiated there, but I
am unsure how I should proceed working around this.
Here is the output of the vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved
And here is the output of the error
---=======================
BUILDER: Building IP cmplx_mul
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source
/workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log
cmplx_mul.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the
following file is locked:
/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the
following file is locked:
/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part
xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products
for Synthesis target. These output products could be required for
synthesis, please generate the output products using the generate_target or
synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources
specified
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location:
/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
make[1]: *** [/rfnoc-foo/fpga//ip/cmplx_mul/Makefile.inc:21:
LIB_IP_CMPLX_MUL_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
Hi,
This is the output of source setupenv.sh
Setting up a 64-bit FPGA build environment for the USRP-X3x0...
- Vivado: Found (/tools/Xilinx/Vivado/2021.1/bin)
Installed version is Vivado v2021.1_AR76780 (64-bit)
Environment successfully initialized.
I ended up opening the hbXX cores with vivado and updating them to my version. That makes the firmware compile. However, it complains a lot with critical warnings about FIR filters during compile. Specifically, I read this line that makes me worry:
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/lorenzo/uhd/fpga/usrp3/top/UHD_revamp.gen/sources_1/ip/axi_hb31/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module.
Note that the folder UHD_revamp is the vivado project I used to import the xci files for updating. Maybe there is a better way to open the .xci without creating a new project?
Thanks,
Lorenzo
From: Wade Fife wade.fife@ettus.com
Sent: Thursday, February 2, 2023 7:37 PM
To: Minutolo, Lorenzo minutolo@caltech.edu
Cc: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Hi Lorenzo,
I tried your steps but couldn't reproduce the issue you're seeing. I wonder if somehow the patch is not being picked up, or perhaps you somehow have stale build files. Can you run the following?
cd fpga/usrp3/top/x300/
source setupenv.sh
What's the output of setupenv.sh?
At this point you can try:
make cleanall
make X300_HG
Typically the IP locked issue happens when there is a mismatch between the version of Vivado that was used to generate the IP and the version of Vivado that is being used to build the FPGA. You can see the Vivado version that was used to generate the IP here:
https://github.com/EttusResearch/uhd/blob/UHD-4.4/fpga/usrp3/lib/ip/axi_hb31/axi_hb31.xci#L247
You can see the version of the version of Vivado you're using to build the FPGA when you run "source setupenv.sh". It is also possible to open the IP in Vivado and unlock it by fixing whatever version mismatch it sees, but you should be building with 2021.1_AR76780 or else other IP will give you similar problems.
Please double check that you don't have changes or untracked files in your repo (running git status should tell you) or old builds laying around (make cleanall should remove those). And make sure that setupenv.sh reports v2021.1_AR76780. If you have multiple patches or the same patch installed in multiple places, that might also cause a version mismatch.
Wade
On Tue, Jan 31, 2023 at 5:06 PM Minutolo, Lorenzo <minutolo@caltech.edumailto:minutolo@caltech.edu> wrote:
After reading about this conversation on the mailing list https://lists.ettus.com/empathy/thread/DGJBPK6YADKXM2ETKPEVQQ7F5ALJCIDD
I went ahead and erased my UHD distribution folder and started from scratch. Here is how to reproduce what I did:
Given a patched version of Vivado installed on the system:
/tools/Xilinx/Vivado/2021.1/bin/vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
Commands:
git clone git clone https://github.com/EttusResearch/uhd.git
cd uhd
git checkout UHD-4.4
<optional>
cd host
mkdir build && cd build
cmake ..
make -j10
sudo make install
cd ../..
<end optional>
cd fpga/usrp3/top/x300/
rfnoc_image_builder -c -d x300 -y ./x300_rfnoc_image_core.yml -t X300_HG -p /tools/Xilinx/Vivado/
This results in the error reported below.
From: Minutolo, Lorenzo <minutolo@caltech.edumailto:minutolo@caltech.edu>
Sent: Tuesday, January 31, 2023 2:20 PM
To: jmaloyan@umass.edumailto:jmaloyan@umass.edu <jmaloyan@umass.edumailto:jmaloyan@umass.edu>; usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com>
Subject: [USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
I tried installing Vivado 2021.1 and applying the right patch, using UHD-4.4 I still get the following error message:
---=======================
BUILDER: Building IP axi_hb31
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31
BUILDER: Retargeting IP to part kintex7/xc7k325t/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /home/lorenzo/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log axi_hb31.log -nojournal
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
[00:00:04] Current task: Initialization +++ Current Phase: Starting
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
[00:00:04] Current task: Initialization +++ Current Phase: Finished
[00:00:04] Executing Tcl: synth_design -top axi_hb31 -part xc7k325tffg900-2 -mode out_of_context
[00:00:04] Starting Synthesis Command
[00:00:04] Current task: Synthesis +++ Current Phase: Starting
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
Currently looking for a workaround before reverting to 2019.1 and UHD 4.2
Lorenzo
From: Minutolo, Lorenzo <minutolo@caltech.edumailto:minutolo@caltech.edu>
Sent: Tuesday, January 31, 2023 11:48 AM
To: jmaloyan@umass.edumailto:jmaloyan@umass.edu <jmaloyan@umass.edumailto:jmaloyan@umass.edu>; usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com>
Subject: [USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Same here.
Since switching to Vivado 2021.1 and UHD-4.3 even compiling the stock firmware results in [IP_Flow 19-2162] IP 'axi_hb31' is locked.
Apparently, this error is well known https://support.xilinx.com/s/article/58832?language=en_US
I'm trying to switch to UHD 4.4 to see if this error goes away. Everything was working really well in UHD-4.2 and Vivado 2019.1.
Best,
Lorenzo
From: jmaloyan@umass.edumailto:jmaloyan@umass.edu <jmaloyan@umass.edumailto:jmaloyan@umass.edu>
Sent: Friday, January 27, 2023 2:17 PM
To: usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com>
Subject: [USRP-users] Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Hello,
I have run into an issue when trying to synthesize the “gain” RFNoC as described in the tutorial here https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the verilog file “rfnoc_block_gain.v”, the module is instantiated there, but I am unsure how I should proceed working around this.
Here is the output of the vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved
And here is the output of the error
---=======================
BUILDER: Building IP cmplx_mul
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log cmplx_mul.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
make[1]: *** [/rfnoc-foo/fpga//ip/cmplx_mul/Makefile.inc:21: LIB_IP_CMPLX_MUL_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
USRP-users mailing list -- usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.commailto:usrp-users-leave@lists.ettus.com
Setupenv says you're using 2021.1_AR76780. The hbXX cores are already set
to 2021.1_AR76780, since UHD 4.3, so there should be nothing to update
unless you have old file versions.
That critical warning about axi_hb31 is expected.
Wade
On Fri, Feb 3, 2023 at 12:48 PM Minutolo, Lorenzo minutolo@caltech.edu
wrote:
Hi,
This is the output of source setupenv.sh
Setting up a 64-bit FPGA build environment for the USRP-X3x0...
- Vivado: Found (/tools/Xilinx/Vivado/2021.1/bin)
Installed version is Vivado v2021.1_AR76780 (64-bit)
Environment successfully initialized.
I ended up opening the hbXX cores with vivado and updating them to my
version. That makes the firmware compile. However, it complains a lot with
critical warnings about FIR filters during compile. Specifically, I read
this line that makes me worry:
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb31'.
The XDC file
/home/lorenzo/uhd/fpga/usrp3/top/UHD_revamp.gen/sources_1/ip/axi_hb31/constraints/fir_compiler_v7_2.xdc
will not be read for any cell of this module.
Note that the folder UHD_revamp is the vivado project I used to import the
xci files for updating. Maybe there is a better way to open the .xci
without creating a new project?
Thanks,
Lorenzo
From: Wade Fife wade.fife@ettus.com
Sent: Thursday, February 2, 2023 7:37 PM
To: Minutolo, Lorenzo minutolo@caltech.edu
Cc: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Re: Error when synthesizing example OOT block
: IP "cmplx_mul" is locked
Hi Lorenzo,
I tried your steps but couldn't reproduce the issue you're seeing. I
wonder if somehow the patch is not being picked up, or perhaps you somehow
have stale build files. Can you run the following?
cd fpga/usrp3/top/x300/
source setupenv.sh
What's the output of setupenv.sh?
At this point you can try:
make cleanall
make X300_HG
Typically the IP locked issue happens when there is a mismatch between the
version of Vivado that was used to generate the IP and the version of
Vivado that is being used to build the FPGA. You can see the Vivado version
that was used to generate the IP here:
https://github.com/EttusResearch/uhd/blob/UHD-4.4/fpga/usrp3/lib/ip/axi_hb31/axi_hb31.xci#L247
You can see the version of the version of Vivado you're using to build the
FPGA when you run "source setupenv.sh". It is also possible to open the IP
in Vivado and unlock it by fixing whatever version mismatch it sees, but
you should be building with 2021.1_AR76780 or else other IP will give you
similar problems.
Please double check that you don't have changes or untracked files in your
repo (running git status should tell you) or old builds laying around
(make cleanall should remove those). And make sure that setupenv.sh
reports v2021.1_AR76780. If you have multiple patches or the same patch
installed in multiple places, that might also cause a version mismatch.
Wade
On Tue, Jan 31, 2023 at 5:06 PM Minutolo, Lorenzo minutolo@caltech.edu
wrote:
After reading about this conversation on the mailing list
https://lists.ettus.com/empathy/thread/DGJBPK6YADKXM2ETKPEVQQ7F5ALJCIDD
I went ahead and erased my UHD distribution folder and started from
scratch. Here is how to reproduce what I did:
Given a patched version of Vivado installed on the system:
/tools/Xilinx/Vivado/2021.1/bin/vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
Commands:
git clone git clone https://github.com/EttusResearch/uhd.git
cd uhd
git checkout UHD-4.4
<optional>
cd host
mkdir build && cd build
cmake ..
make -j10
sudo make install
cd ../..
<end optional>
cd fpga/usrp3/top/x300/
rfnoc_image_builder -c -d x300 -y ./x300_rfnoc_image_core.yml -t X300_HG
-p /tools/Xilinx/Vivado/
This results in the error reported below.
From: Minutolo, Lorenzo minutolo@caltech.edu
Sent: Tuesday, January 31, 2023 2:20 PM
To: jmaloyan@umass.edu jmaloyan@umass.edu; usrp-users@lists.ettus.com
usrp-users@lists.ettus.com
Subject: [USRP-users] Re: Error when synthesizing example OOT block :
IP "cmplx_mul" is locked
I tried installing Vivado 2021.1 and applying the right patch, using
UHD-4.4 I still get the following error message:
---=======================
BUILDER: Building IP axi_hb31
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31
BUILDER: Retargeting IP to part kintex7/xc7k325t/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source
/home/lorenzo/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log
axi_hb31.log -nojournal
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
[00:00:04] Current task: Initialization +++ Current Phase: Starting
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the
following file is locked:
/home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the
following file is locked:
/home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
[00:00:04] Current task: Initialization +++ Current Phase: Finished
[00:00:04] Executing Tcl: synth_design -top axi_hb31 -part
xc7k325tffg900-2 -mode out_of_context
[00:00:04] Starting Synthesis Command
[00:00:04] Current task: Synthesis +++ Current Phase: Starting
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products
for Synthesis target. These output products could be required for
synthesis, please generate the output products using the generate_target or
synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources
specified
Currently looking for a workaround before reverting to 2019.1 and UHD 4.2
Lorenzo
From: Minutolo, Lorenzo minutolo@caltech.edu
Sent: Tuesday, January 31, 2023 11:48 AM
To: jmaloyan@umass.edu jmaloyan@umass.edu; usrp-users@lists.ettus.com
usrp-users@lists.ettus.com
Subject: [USRP-users] Re: Error when synthesizing example OOT block :
IP "cmplx_mul" is locked
Same here.
Since switching to Vivado 2021.1 and UHD-4.3 even compiling the stock
firmware results in [IP_Flow 19-2162] IP 'axi_hb31' is locked.
Apparently, this error is well known
https://support.xilinx.com/s/article/58832?language=en_US
I'm trying to switch to UHD 4.4 to see if this error goes away. Everything
was working really well in UHD-4.2 and Vivado 2019.1.
Best,
Lorenzo
From: jmaloyan@umass.edu jmaloyan@umass.edu
Sent: Friday, January 27, 2023 2:17 PM
To: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: [USRP-users] Error when synthesizing example OOT block : IP
"cmplx_mul" is locked
Hello,
I have run into an issue when trying to synthesize the “gain” RFNoC as
described in the tutorial here
https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the
verilog file “rfnoc_block_gain.v”, the module is instantiated there, but I
am unsure how I should proceed working around this.
Here is the output of the vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved
And here is the output of the error
---=======================
BUILDER: Building IP cmplx_mul
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source
/workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log
cmplx_mul.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the
following file is locked:
/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the
following file is locked:
/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part
xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products
for Synthesis target. These output products could be required for
synthesis, please generate the output products using the generate_target or
synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources
specified
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location:
/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
make[1]: *** [/rfnoc-foo/fpga//ip/cmplx_mul/Makefile.inc:21:
LIB_IP_CMPLX_MUL_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
USRP-users mailing list -- usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.com
I was puzzled too.
Tried on a fresh ubuntu install and still gives me the same error.
Maybe I am doing something wrong in the install process? The compiled firmware works as expected (without FIRs).
Not a problem since I don't plan to use the FIR compiler. Just wanted to put it out there.
Lorenzo
From: Wade Fife wade.fife@ettus.com
Sent: Friday, February 3, 2023 11:27 AM
To: Minutolo, Lorenzo minutolo@caltech.edu
Cc: usrp-users@lists.ettus.com usrp-users@lists.ettus.com
Subject: Re: [USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Setupenv says you're using 2021.1_AR76780. The hbXX cores are already set to 2021.1_AR76780, since UHD 4.3, so there should be nothing to update unless you have old file versions.
That critical warning about axi_hb31 is expected.
Wade
On Fri, Feb 3, 2023 at 12:48 PM Minutolo, Lorenzo <minutolo@caltech.edumailto:minutolo@caltech.edu> wrote:
Hi,
This is the output of source setupenv.sh
Setting up a 64-bit FPGA build environment for the USRP-X3x0...
- Vivado: Found (/tools/Xilinx/Vivado/2021.1/bin)
Installed version is Vivado v2021.1_AR76780 (64-bit)
Environment successfully initialized.
I ended up opening the hbXX cores with vivado and updating them to my version. That makes the firmware compile. However, it complains a lot with critical warnings about FIR filters during compile. Specifically, I read this line that makes me worry:
CRITICAL WARNING: [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/lorenzo/uhd/fpga/usrp3/top/UHD_revamp.gen/sources_1/ip/axi_hb31/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module.
Note that the folder UHD_revamp is the vivado project I used to import the xci files for updating. Maybe there is a better way to open the .xci without creating a new project?
Thanks,
Lorenzo
From: Wade Fife <wade.fife@ettus.commailto:wade.fife@ettus.com>
Sent: Thursday, February 2, 2023 7:37 PM
To: Minutolo, Lorenzo <minutolo@caltech.edumailto:minutolo@caltech.edu>
Cc: usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com>
Subject: Re: [USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Hi Lorenzo,
I tried your steps but couldn't reproduce the issue you're seeing. I wonder if somehow the patch is not being picked up, or perhaps you somehow have stale build files. Can you run the following?
cd fpga/usrp3/top/x300/
source setupenv.sh
What's the output of setupenv.sh?
At this point you can try:
make cleanall
make X300_HG
Typically the IP locked issue happens when there is a mismatch between the version of Vivado that was used to generate the IP and the version of Vivado that is being used to build the FPGA. You can see the Vivado version that was used to generate the IP here:
https://github.com/EttusResearch/uhd/blob/UHD-4.4/fpga/usrp3/lib/ip/axi_hb31/axi_hb31.xci#L247
You can see the version of the version of Vivado you're using to build the FPGA when you run "source setupenv.sh". It is also possible to open the IP in Vivado and unlock it by fixing whatever version mismatch it sees, but you should be building with 2021.1_AR76780 or else other IP will give you similar problems.
Please double check that you don't have changes or untracked files in your repo (running git status should tell you) or old builds laying around (make cleanall should remove those). And make sure that setupenv.sh reports v2021.1_AR76780. If you have multiple patches or the same patch installed in multiple places, that might also cause a version mismatch.
Wade
On Tue, Jan 31, 2023 at 5:06 PM Minutolo, Lorenzo <minutolo@caltech.edumailto:minutolo@caltech.edu> wrote:
After reading about this conversation on the mailing list https://lists.ettus.com/empathy/thread/DGJBPK6YADKXM2ETKPEVQQ7F5ALJCIDD
I went ahead and erased my UHD distribution folder and started from scratch. Here is how to reproduce what I did:
Given a patched version of Vivado installed on the system:
/tools/Xilinx/Vivado/2021.1/bin/vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
Commands:
git clone git clone https://github.com/EttusResearch/uhd.git
cd uhd
git checkout UHD-4.4
<optional>
cd host
mkdir build && cd build
cmake ..
make -j10
sudo make install
cd ../..
<end optional>
cd fpga/usrp3/top/x300/
rfnoc_image_builder -c -d x300 -y ./x300_rfnoc_image_core.yml -t X300_HG -p /tools/Xilinx/Vivado/
This results in the error reported below.
From: Minutolo, Lorenzo <minutolo@caltech.edumailto:minutolo@caltech.edu>
Sent: Tuesday, January 31, 2023 2:20 PM
To: jmaloyan@umass.edumailto:jmaloyan@umass.edu <jmaloyan@umass.edumailto:jmaloyan@umass.edu>; usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com>
Subject: [USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
I tried installing Vivado 2021.1 and applying the right patch, using UHD-4.4 I still get the following error message:
---=======================
BUILDER: Building IP axi_hb31
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31
BUILDER: Retargeting IP to part kintex7/xc7k325t/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /home/lorenzo/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log axi_hb31.log -nojournal
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
[00:00:04] Current task: Initialization +++ Current Phase: Starting
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/lorenzo/uhd/fpga/usrp3/top/x300/build-ip/xc7k325tffg900-2/axi_hb31/axi_hb31.xci
[00:00:04] Current task: Initialization +++ Current Phase: Finished
[00:00:04] Executing Tcl: synth_design -top axi_hb31 -part xc7k325tffg900-2 -mode out_of_context
[00:00:04] Starting Synthesis Command
[00:00:04] Current task: Synthesis +++ Current Phase: Starting
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
Currently looking for a workaround before reverting to 2019.1 and UHD 4.2
Lorenzo
From: Minutolo, Lorenzo <minutolo@caltech.edumailto:minutolo@caltech.edu>
Sent: Tuesday, January 31, 2023 11:48 AM
To: jmaloyan@umass.edumailto:jmaloyan@umass.edu <jmaloyan@umass.edumailto:jmaloyan@umass.edu>; usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com>
Subject: [USRP-users] Re: Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Same here.
Since switching to Vivado 2021.1 and UHD-4.3 even compiling the stock firmware results in [IP_Flow 19-2162] IP 'axi_hb31' is locked.
Apparently, this error is well known https://support.xilinx.com/s/article/58832?language=en_US
I'm trying to switch to UHD 4.4 to see if this error goes away. Everything was working really well in UHD-4.2 and Vivado 2019.1.
Best,
Lorenzo
From: jmaloyan@umass.edumailto:jmaloyan@umass.edu <jmaloyan@umass.edumailto:jmaloyan@umass.edu>
Sent: Friday, January 27, 2023 2:17 PM
To: usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com>
Subject: [USRP-users] Error when synthesizing example OOT block : IP "cmplx_mul" is locked
Hello,
I have run into an issue when trying to synthesize the “gain” RFNoC as described in the tutorial here https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
I get an error that the module cmplx mul is locked. I found that in the verilog file “rfnoc_block_gain.v”, the module is instantiated there, but I am unsure how I should proceed working around this.
Here is the output of the vivado -version
Vivado v2021.1_AR76780 (64-bit)
SW Build 3247384 on Thu Jun 10 19:36:07 MDT 2021
IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
Copyright 1986-2021 Xilinx, Inc. All Rights Reserved
And here is the output of the error
---=======================
BUILDER: Building IP cmplx_mul
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
BUILDER: Retargeting IP to part zynq/xc7z100/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /workarea/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log cmplx_mul.log -nojournal
[00:00:05] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xci
[00:00:05] Current task: Initialization +++ Current Phase: Finished
[00:00:05] Executing Tcl: synth_design -top cmplx_mul -part xc7z100ffg900-2 -mode out_of_context
[00:00:05] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'cmplx_mul' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
[00:00:06] Current task: Synthesis +++ Current Phase: Starting
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul/cmplx_mul.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:06] Current task: Synthesis +++ Current Phase: Finished
[00:00:06] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location: /workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/cmplx_mul
make[1]: *** [/rfnoc-foo/fpga//ip/cmplx_mul/Makefile.inc:21: LIB_IP_CMPLX_MUL_TRGT] Error 1
make[1]: Leaving directory '/workarea/uhd/fpga/usrp3/top/n3xx'
make: *** [Makefile:90: N3X0_IP] Error 2
USRP-users mailing list -- usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com
To unsubscribe send an email to usrp-users-leave@lists.ettus.commailto:usrp-users-leave@lists.ettus.com