Is this a new cloning/installation of the code base, or are you using an old commit/release? You can see that the file is provided from the code base: https://github.com/EttusResearch/fpga/tree/maint/usrp3/sim/general Cheers, - Nicolas On Mon, Jan 30, 2017 at 12:39 PM, Christian Blümm via USRP-users < usrp-users@lists.ettus.com> wrote: > Dear all, > > I have problems setting up the XSIM simulator for rfnoc testbenches (I > could not run the standard testbenches noc_block_fft_tb and > noc_block_skeleton_tb). I do not have Modelsim. > It seems it's missing the "sim_exec_report.vh" file in the makefile. > I'm using Vivado 2015.4 and the latest UHD version > UHD_4.0.0.rfnoc-devel-162-g335a1317 . I'm able to initialize setupenv.sh > and set up an FPGA RFNoC design via "make X310_RFNOC_HG GUI=1". > > Here's what I get: > > chris@chris-N76VZ:~/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_skeleton_tb$ *source > ~/uhd/fpga-src/usrp3/top/x300/setupenv.sh* > Setting up a 64-bit FPGA build environment for the USRP-X3x0... > - Vivado: Found (/home/chris/Xilinx/Vivado/2015.4/bin) > - Vivado HLS: Not found in /opt/Xilinx/Vivado_HLS (WARNING.. HLS build > targets will not work) > Environment successfully initialized. > > chris@chris-N76VZ:~/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_skeleton_tb$ *make > GUI=1 xsim* > BUILDER: Checking tools... > * GNU bash, version 4.3.11(1)-release (x86_64-pc-linux-gnu) > * Python 2.7.6 > * Vivado v2015.4 (64-bit) > make: *** No rule to make target `/home/chris/uhd/fpga-src/ > usrp3/sim/general/sim_exec_report.vh', needed by `xsim'. Stop. > > I digged into the Makefiles but couldn't find the relation to this > sim_exec_report.vh file yet. Any ideas? > Many thanks, > Christian > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

the line > 7. However, this output is rather odd, and I it appears that the testbench > process is unable to find that file. Do you have a sim_exec_report.vh file > in /home/chris/uhd/fpga-src/usrp3/sim/general/? > > Is this a new cloning/installation of the code base, or are you using an > old commit/release? You can see that the file is provided from the code > base: https://github.com/EttusResearch/fpga/tree/maint/usrp3/sim/general > > Cheers, > - Nicolas > > On Mon, Jan 30, 2017 at 12:39 PM, Christian Blümm via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Dear all, >> >> I have problems setting up the XSIM simulator for rfnoc testbenches (I >> could not run the standard testbenches noc_block_fft_tb and >> noc_block_skeleton_tb). I do not have Modelsim. >> It seems it's missing the "sim_exec_report.vh" file in the makefile. >> I'm using Vivado 2015.4 and the latest UHD version >> UHD_4.0.0.rfnoc-devel-162-g335a1317 . I'm able to initialize setupenv.sh >> and set up an FPGA RFNoC design via "make X310_RFNOC_HG GUI=1". >> >> Here's what I get: >> >> chris@chris-N76VZ:~/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_skeleton_tb$ *source >> ~/uhd/fpga-src/usrp3/top/x300/setupenv.sh* >> Setting up a 64-bit FPGA build environment for the USRP-X3x0... >> - Vivado: Found (/home/chris/Xilinx/Vivado/2015.4/bin) >> - Vivado HLS: Not found in /opt/Xilinx/Vivado_HLS (WARNING.. HLS build >> targets will not work) >> Environment successfully initialized. >> >> chris@chris-N76VZ:~/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_skeleton_tb$ *make >> GUI=1 xsim* >> BUILDER: Checking tools... >> * GNU bash, version 4.3.11(1)-release (x86_64-pc-linux-gnu) >> * Python 2.7.6 >> * Vivado v2015.4 (64-bit) >> make: *** No rule to make target `/home/chris/uhd/fpga-src/usrp >> 3/sim/general/sim_exec_report.vh', needed by `xsim'. Stop. >> >> I digged into the Makefiles but couldn't find the relation to this >> sim_exec_report.vh file yet. Any ideas? >> Many thanks, >> Christian >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

et me know how? Also does it have a single DDC or multiple one? > > > BR > > Snehasish > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >

_____________ This message including any attachments may contain confidential information, according to our Information Security Management System, and intended solely for a specific individual to whom they are addressed. Any unauthorised copy, disclosure or distribution of this message is strictly forbidden. If you have received this transmission in error, please notify the sender immediately and delete it. ______________________ Este mensaje, y en su caso, cualquier fichero anexo al mismo, puede contener informacion clasificada por su emisor como confidencial en el marco de su Sistema de Gestion de Seguridad de la Informacion siendo para uso exclusivo del destinatario, quedando prohibida su divulgacion copia o distribucion a terceros sin la autorizacion expresa del remitente. Si Vd. ha recibido este mensaje erroneamente, se ruega lo notifique al remitente y proceda a su borrado. Gracias por su colaboracion. ______________________

his works only inside a sandboxed version of UHD (from branch rfnoc-devel). If I run uhd_usrp_probe from my system version (compiled from the last release of maint branch), the new block appears only as Block_0. Is there any way for UHD v3.1.0.1 to recognize my block properly (beyond its name, I'm of course intersted in it recognizing all its ports and registers). I tried copying the .xml declaration file to /usr/local/share/uhd/rfnoc/blocks/, but that doesn't seem to be enough. Should I recompile some library? Or is there no other way than using rfnoc-devel? Thank you again, Leo

anager encountered a recoverable error in init. Loading the "unknown" daughterboard implementations to continue. The daughterboard cannot operate until this error is resolved. AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 in double dbsrx::set_lo_freq(double) at /home/carlos/rfnoc/uhd/host/lib/usrp/dboard/db_dbsrx.cpp:305 _____________________________________________________ / | Device: USRP1 Device | _____________________________________________________ | / | | Mboard: USRP1 | | serial: 479b9db3 | | | | Time sources: none | | Clock sources: internal | | Sensors: | | _____________________________________________________ | | / | | | RX DSP: 0 | | | | | | Freq range: -32.000 to 32.000 MHz | | _____________________________________________________ | | / | | | RX DSP: 1 | | | | | | Freq range: -32.000 to 32.000 MHz | | _____________________________________________________ | | / | | | RX Dboard: A | | | ID: DBSRX (0x0002) | | | _____________________________________________________ | | | / | | | | RX Frontend: 0 | | | | Name: Unknown (0xffff) - 0 | | | | Antennas: | | | | Sensors: | | | | Freq range: 0.000 to 0.000 MHz | | | | Gain Elements: None | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | RX Codec: A | | | | Name: ad9522 | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB | | _____________________________________________________ | | / | | | RX Dboard: B | | | _____________________________________________________ | | | / | | | | RX Frontend: 0 | | | | Name: Unknown (0xffff) - 0 | | | | Antennas: | | | | Sensors: | | | | Freq range: 0.000 to 0.000 MHz | | | | Gain Elements: None | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | RX Codec: B | | | | Name: ad9522 | | | | Gain range pga: 0.0 to 20.0 step 1.0 dB | | _____________________________________________________ | | / | | | TX DSP: 0 | | | | | | Freq range: -44.000 to 44.000 MHz | | _____________________________________________________ | | / | | | TX DSP: 1 | | | | | | Freq range: -44.000 to 44.000 MHz | | _____________________________________________________ | | / | | | TX Dboard: A | | | _____________________________________________________ | | | / | | | | TX Frontend: 0 | | | | Name: Unknown (0xffff) - 0 | | | | Antennas: | | | | Sensors: | | | | Freq range: 0.000 to 0.000 MHz | | | | Gain Elements: None | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | TX Codec: A | | | | Name: ad9522 | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB | | _____________________________________________________ | | / | | | TX Dboard: B | | | _____________________________________________________ | | | / | | | | TX Frontend: 0 | | | | Name: Unknown (0xffff) - 0 | | | | Antennas: | | | | Sensors: | | | | Freq range: 0.000 to 0.000 MHz | | | | Gain Elements: None | | | | Bandwidth range: 0.0 to 0.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | TX Codec: B | | | | Name: ad9522 | | | | Gain range pga: -20.0 to 0.0 step 0.1 dB And the same in GNURadio: Executing: /usr/bin/python2 -u /home/carlos/top_block.py [32;1m[INFO] [UHD] [39;0mlinux; GNU C++ version 7.3.0; Boost_106501; UHD_4.0.0.rfnoc-devel-702-geec24d7b [32;1m[INFO] [USRP1] [39;0mOpening a USRP1 device... [32;1m[INFO] [USRP1] [39;0mUsing FPGA clock rate of 64.000000MHz... [31;0m[ERROR] [DBMGR] [39;0mThe daughterboard manager encountered a recoverable error in init. Loading the "unknown" daughterboard implementations to continue. The daughterboard cannot operate until this error is resolved. AssertionError: m and ref_clock/m >= 1e6 and ref_clock/m <= 2.5e6 in double dbsrx::set_lo_freq(double) at /home/carlos/rfnoc/uhd/host/lib/usrp/dboard/db_dbsrx.cpp:305 [33;1m[WARNING] [MULTI_USRP] [39;0mSetting IQ imbalance compensation is not possible on this device. INFO: Audio sink arch: alsa aUaU

ng pc board. Included in each kit: 1 HP 10811a-60111 1 sma unknown 5v active patch gps L1 antenna 1 HP 58535a gps active splitter 1 Motorola M12+T gps receiver The built kit gets an HP rack mount enclosure with a LCD display of the efc voltage. Feel free to use the boards inside, but as you will see, it was my first attempt at a partial kit where YOU the builder must buy to spec and then integrate according to a plan. Looks like hell. Works ok, though.. Would like to trade for equipment. Particularly microwave attenuators, mixers, preamps. Will trade + cash for a signal generator good to 18 GHz. Kit one (built board with enclosure and power supply. Ask for photos.) $250 Kit two $210 All reasonable offers considered.

al out of it's socket.) It worked and I made several contacts. AND I saved money by not buying a chassis. Sometimes I wonder how I've managed to live long enough to become this ancient. Burt, K6OQK >Behalf Of paul swed > >Joe >Thats really a silly statement. The issue is this, we tech types put things >in rows and columns. But true artists use dead bug style with lots of wire >and parts flying everyplace. >Put the whole glob in a picture frame and you have a seriously worthy piece >of art. How could your wife complain? Plus you get time out of it. Its all >about how you sell it. >Regards >Paul > Burt I. Weiner Associates Broadcast Technical Services Glendale, California U.S.A. biwa@att.net www.biwa.cc K6OQK