Dear all, I have problems setting up the XSIM simulator for rfnoc testbenches (I could not run the standard testbenches noc_block_fft_tb and noc_block_skeleton_tb). I do not have Modelsim. It seems it's missing the "sim_exec_report.vh" file in the makefile. I'm using Vivado 2015.4 and the latest UHD version UHD_4.0.0.rfnoc-devel-162-g335a1317 . I'm able to initialize setupenv.sh and set up an FPGA RFNoC design via "make X310_RFNOC_HG GUI=1". Here's what I get: chris@chris-N76VZ:~/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_skeleton_tb$ source ~/uhd/fpga-src/usrp3/top/x300/setupenv.sh Setting up a 64-bit FPGA build environment for the USRP-X3x0... - Vivado: Found (/home/chris/Xilinx/Vivado/2015.4/bin) - Vivado HLS: Not found in /opt/Xilinx/Vivado_HLS (WARNING.. HLS build targets will not work) Environment successfully initialized. chris@chris-N76VZ:~/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_skeleton_tb$ make GUI=1 xsim BUILDER: Checking tools... * GNU bash, version 4.3.11(1)-release (x86_64-pc-linux-gnu) * Python 2.7.6 * Vivado v2015.4 (64-bit) make: *** No rule to make target `/home/chris/uhd/fpga-src/usrp3/sim/general/sim_exec_report.vh', needed by `xsim'. Stop. I digged into the Makefiles but couldn't find the relation to this sim_exec_report.vh file yet. Any ideas? Many thanks, Christian

Hello Christian, the sim_exec_report is included directly in the testbenches. In the case of the noc_block_skeleton_tb.sv, you can see it is included in the line 7. However, this output is rather odd, and I it appears that the testbench process is unable to find that file. Do you have a sim_exec_report.vh file in /home/chris/uhd/fpga-src/usrp3/sim/general/? Is this a new cloning/installation of the code base, or are you using an old commit/release? You can see that the file is provided from the code base: https://github.com/EttusResearch/fpga/tree/maint/usrp3/sim/general Cheers, - Nicolas On Mon, Jan 30, 2017 at 12:39 PM, Christian Blümm via USRP-users < usrp-users@lists.ettus.com> wrote: > Dear all, > > I have problems setting up the XSIM simulator for rfnoc testbenches (I > could not run the standard testbenches noc_block_fft_tb and > noc_block_skeleton_tb). I do not have Modelsim. > It seems it's missing the "sim_exec_report.vh" file in the makefile. > I'm using Vivado 2015.4 and the latest UHD version > UHD_4.0.0.rfnoc-devel-162-g335a1317 . I'm able to initialize setupenv.sh > and set up an FPGA RFNoC design via "make X310_RFNOC_HG GUI=1". > > Here's what I get: > > chris@chris-N76VZ:~/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_skeleton_tb$ *source > ~/uhd/fpga-src/usrp3/top/x300/setupenv.sh* > Setting up a 64-bit FPGA build environment for the USRP-X3x0... > - Vivado: Found (/home/chris/Xilinx/Vivado/2015.4/bin) > - Vivado HLS: Not found in /opt/Xilinx/Vivado_HLS (WARNING.. HLS build > targets will not work) > Environment successfully initialized. > > chris@chris-N76VZ:~/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_skeleton_tb$ *make > GUI=1 xsim* > BUILDER: Checking tools... > * GNU bash, version 4.3.11(1)-release (x86_64-pc-linux-gnu) > * Python 2.7.6 > * Vivado v2015.4 (64-bit) > make: *** No rule to make target `/home/chris/uhd/fpga-src/ > usrp3/sim/general/sim_exec_report.vh', needed by `xsim'. Stop. > > I digged into the Makefiles but couldn't find the relation to this > sim_exec_report.vh file yet. Any ideas? > Many thanks, > Christian > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

Hi Christian, What OS are you using? Have you set bash as your default system shell? Jonathon On Mon, Jan 30, 2017 at 8:11 AM, Nicolas Cuervo via USRP-users < usrp-users@lists.ettus.com> wrote: > Hello Christian, > > the sim_exec_report is included directly in the testbenches. In the case > of the noc_block_skeleton_tb.sv, you can see it is included in the line > 7. However, this output is rather odd, and I it appears that the testbench > process is unable to find that file. Do you have a sim_exec_report.vh file > in /home/chris/uhd/fpga-src/usrp3/sim/general/? > > Is this a new cloning/installation of the code base, or are you using an > old commit/release? You can see that the file is provided from the code > base: https://github.com/EttusResearch/fpga/tree/maint/usrp3/sim/general > > Cheers, > - Nicolas > > On Mon, Jan 30, 2017 at 12:39 PM, Christian Blümm via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Dear all, >> >> I have problems setting up the XSIM simulator for rfnoc testbenches (I >> could not run the standard testbenches noc_block_fft_tb and >> noc_block_skeleton_tb). I do not have Modelsim. >> It seems it's missing the "sim_exec_report.vh" file in the makefile. >> I'm using Vivado 2015.4 and the latest UHD version >> UHD_4.0.0.rfnoc-devel-162-g335a1317 . I'm able to initialize setupenv.sh >> and set up an FPGA RFNoC design via "make X310_RFNOC_HG GUI=1". >> >> Here's what I get: >> >> chris@chris-N76VZ:~/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_skeleton_tb$ *source >> ~/uhd/fpga-src/usrp3/top/x300/setupenv.sh* >> Setting up a 64-bit FPGA build environment for the USRP-X3x0... >> - Vivado: Found (/home/chris/Xilinx/Vivado/2015.4/bin) >> - Vivado HLS: Not found in /opt/Xilinx/Vivado_HLS (WARNING.. HLS build >> targets will not work) >> Environment successfully initialized. >> >> chris@chris-N76VZ:~/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_skeleton_tb$ *make >> GUI=1 xsim* >> BUILDER: Checking tools... >> * GNU bash, version 4.3.11(1)-release (x86_64-pc-linux-gnu) >> * Python 2.7.6 >> * Vivado v2015.4 (64-bit) >> make: *** No rule to make target `/home/chris/uhd/fpga-src/usrp >> 3/sim/general/sim_exec_report.vh', needed by `xsim'. Stop. >> >> I digged into the Makefiles but couldn't find the relation to this >> sim_exec_report.vh file yet. Any ideas? >> Many thanks, >> Christian >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >