However she is constantly wiping the top since everything is by touch...set temp, turn up or down so the black top is covered in seconds with finger prints and she is an obsessive neat freak! I would think that glass top would be slippery with the least movement? At least steel grates are far less so and it be useless if the boat is in even a small sea.

Why is the top domed? I assume flat would be easier to manufacture. Why is it not symmetrical? If the top is domed, why not the bottom too? -- These are my opinions, not necessarily my employer's. I hate spam.

David, If I hold my Jupiter in the position where the connector is on the left and the 11577-11 is facing me then the 10kHz is on pin 20 of the connector (top right) and this pin is connected to pin 13 counting from the top right-hand-side of the IC.

include size = 20; $fa=1;$fs=.3; diff() cuboid(size) attach(TOP,TOP,inside=true) cyl(h=size,d=4,rounding=-2,extra=1); // extra adds length to avoid z-fighting [image: image.png] On Fri, Jun 6, 2025 at 4:33 PM Joe Weinpert via Discuss < discuss@lists.openscad.org> wrote: > I want to create a block with a hole in it where the top

. > > > > debadrita@vipl:~$ cd ettus_uhd/uhd/fpga-src/usrp3/top/x300 > > debadrita@vipl:~/ettus_uhd/uhd/fpga-src/usrp3/top/x300$ source > setupenv.sh > > Setting up a 64-bit FPGA build environment for the USRP-X3x0... > > - Vivado: Found (/opt/Xilinx/Vivado_Lab/2015.4/bin) > > - Vivado HLS: Found (/opt/Xilinx/Vivado_HLS/2015.4/bin) > > > > Environment successfully

/usrp3/top/x300/build-ip/xc7k410tffg900-2/one_gig_eth_pcs_pma_example/one_gig_eth_pcs_pma_example.srcs/sources_1/imports/example_design/support/one_gig_eth_pcs_pma_clocking.v': No such file or directory /home/lp78/rfnoc/src/uhd-fpga/usrp3/top/x300/ip/one_gig_eth_pcs_pma/Makefile.inc:46: recipe for target '/home/lp78/rfnoc/src/uhd-fpga/usrp3/top/x300/build-ip/

BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml' CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip/xc7z100ffg900-2/hb47_1to2/hb47_1to2.xml' CRITICAL WARNING: \[IP_Flow 19-4739\] Writing uncustomized BOM file '/workarea/uhd/fpga/usrp3/top/n3xx/build-ip

Marvin said: There should be a shutoff valve at the bottom and top of a sight glass. The upper attachment point for a sight glass is never right at the top of the tank--- it's always an inch or two or more lower.

> > There is a directory called "top": And under that is a subdirectory callled "B200": uhd/fpga-src/usrp3/top/b200 That is the top-level for the B200, and there's a Makefile in there that you'll need to run: make PROJECT_ONLY=1 which will generate a project file for the ISE GUI.

Users/WORK/Desktop/fpga-maint/usrp3/top/b200' make[1]: *** No rule to make target `C:/Users/WORK/Desktop/fpga-maint/usrp3/top/ b200/C:/Users/WORK/Desktop/fpga-maint/usrp3/lib/fifo/axi_demux4.v', needed by `b uild-B210//b200.xise'.