Bruce wrote:

There are many, many ways of getting unnecessarily poor PN
performance from comparators (including Wenzel-style squarers) -- one
has to make sure not to make any of myriad mistakes in both design
and execution.  You didn't say which comparator you tried, or in what
circuit, so I'm not in a position to suggest things to check (or to
confirm that the comparator you tried performs similarly poorly in my
tests, if that is the case).

One sanity check you can try -- disable the filtering on your 6957
eval board.  According to the LT data presented in the chart I
posted, which agrees very closely with my test results, at
10MHz/15dBm there should be essentially no change in the PN compared
to the results you obtained with filtering enabled.  If you see a
significant difference, then something is causing anomalous results.

Best regards,

Charles

ps.  You often respond to one message by replying to a different
message, as you did in this case.  It would be helpful for someone
who just joins a thread, and for continuity in general, if you would
reply to the message to which you are actually responding.  That way,
readers who are new to the thread will have the context they need,
and your interlocutor will have his or her previous message
conveniently available to refer to in any further message.

Hi

There are a wide range of OCXO’s listed for this project. I certainly
do not have a sample of ever single one of them. For the ones that
I do have samples of, a properly done CMOS gate sine to square
converter will not degrade the close in phase noise or ADEV of the OCXO.
Based on TimePod measurements, I believe it would be adequate for
all the ones I’ve seen specs for.

With far removed phase noise spec’d into the “past 180 dbc/Hz” range on
some parts - no logic is going to handle that. Since the CPLD on the board
will floor out well before that, doing a “perfect” conversion and then degrading
it as soon as you hit the bulk logic does not make a lot of sense.

Bob

On Friday, October 23, 2015 05:31:46 AM Charles Steinmetz wrote:

I split the comparator output and feed it to 2 separa

compared

The comparator circuit measured was the front end of David Partridge's
divider. I merely measured the 10MHz output.

I thought that I had made measurements for various filter settings and
input levels. If I did, I don't appear to have saved them. I certainly named
the various TIM files to indicate the filter settings.

I'll try and repeat the measurements for various input levels and filter
settings.
One thing that I have found is that at low offset frequencies the measured
PN is substantially reduced when air currents and other sources of thermal
fluctuations are reduced. Even the effect of a thin piece of paper used as
an air current shield can be easily seen.
With careful shielding from thermal fluctuations I measure the low
frequency offset PN to be substantially lower than the datasheet values.
I've seen this effect with everything for which I've measured the PN.
I may machine a custom housing for the evaluation board rather than just
using an oversize die cast box.
This may take a while as I'll need to check the compatibility of various
hardware/software with Windows 10 that runs on my Quadcore laptop.
Failing that I do have a quad core PC with water cooled CPU that runs
Windows 7.

One problem with comparators when attempting to measure their PN is
that they don't have sufficient output to drive the TimePod input directly.
An amplifier is required. To reduce the Amplifier PN contribution I split the
comparator output and drive a separate amplifier from each splitter output
and then use cross correlation. This makes the amplifier PN much less
critical. Finding low PN amplifiers with relatively low gain ( ~ 10dB or so)
with low distortion at 13dBm or so output is somewhat problematic. A low
noise single transistor discrete amp with 30dB or more reverse isolation
with a gain of 10dBm ought to be feasible at 10MHz.

I dont always have convenient access to my email machine and sometimes
resort to using a browser to compose a reply via my ISP's interface to my
email.
This apparently messes up the reply so it is associated with a different
message to the one I believed I was replying to. This is a fairly recent
phenomenon.

Bruce

Bruce wrote:

The MAX999 and ADCMP600 are the two comparator options noted on
David's schematic.  Both parts suffer from a number of the design and
die-level issues I noted in my previous message, and I have never
obtained particularly good PN with either one.  Also, even the
relatively direct path to the 10MHz output goes through two 'AC04
inverters and an 'AC541 line driver, which contribute additional PN.

Agreed.  Whether or not it is explicitly stated, I take "all
circuitry to be enclosed and protected from drafts, and allowed to
stabilize thermally before testing" as a given with any sensitive
time or voltage circuit.

The spec sheet says both TimePod inputs accept -5 to +20dBm into 50
ohms.  -5dBm is less than 0.4Vp-p, which requires less than +/-4mA
from the source, so a 0-5v comparator output feeding a coupling
capacitor and a 560 ohm series resistor should work fine as long as
the comparator can source and sink at least 4mA.

Alternatively, a 0-5v comparator output could be buffered with three
'AC04 inverters in parallel, or an 'AC line driver -- but that adds
the PN of the gates.

It has just enough effect to correct the very small (<1%) asymmetry
due to the unbalanced drive.  (With no resistor at Point A, the duty
cycle is ~51%/49% high/low.)

According to the simulation, the resistor has no effect on the output
amplitude until it is well below 1k ohms (at 1k ohm, the symmetry has
been WAY overcompensated and the duty cycle is ~45%/55% high/low.

Best regards,

Charles

On Saturday, October 24, 2015 09:03:21 AM Charles Steinmetz wrote:

Partridge's

measured

thermal

as

values.

directly.

The fly in the ointment is that with such low level inputs (the LTC6957-4
evaluation board will deliver +4dBm into 50 ohm) the Timepod phase noise
floor is uncomfortably close to the phase noise floor of the LTC6957.

Not if one uses a pair of drivers one to drive the Timepod Ch0 input and
one to drive the Timepod CH2 input.

attached

Not true even 10k increases the output signal amplitude by 130mV or
2.6%.
However that is smaller than the tilt/sag in the high level output due to
feedthrough via Cbe of the input transistor when it is off.

It would perhaps be useful to measure the PN characteristics of several
comparators and other sine to square converter circuits using a Timepod
or equivalent.

Bruce

I wrote:

Bruce replied:

Bruce is correct, although I don't consider 130mV to be a significant
effect on a 5v logic level.  My fault, I guess, for saying "no"
effect instead of "no significant" or "no material" effect.

But, do we really need to dispute every insignificant, niggling
little detail like this?  Even in science, there must be some
allowance for the use of everyday language instead of requiring
absolute explicit clarification of every possible point, or all
communications would be unbearably tedious from all of the
qualifications.  I say this as someone who is often criticized for
overclarifying to the point of being pedantic and tedious.

There was simply no need, nor excuse, for the prior (incorrect)
suggestion that a resistor to ground from Point "A" would not be
effective in canceling the small asymmetry of the circuit, OR for the
suggestion that such a resistor would be a useful means to adjust the
output amplitude (this because of (i) the concomitant ill effect on
symmetry and (ii) the much more direct and efficacious means of
achieving the result by adjusting R6 or R1 and R2).

Best regards,

Charles

All,

I wish that people had said that the ADCMP600 was a mediocre comparator when I designed the board - I’d have used a better one!

I can't find the post about the design and die level issues in a quick search (I've been off line for a few weeks).

Bruce,

I couldn't find your post about your measurements of my board for the same reason.

Regards,
David Partridge
-----Original Message-----
From: time-nuts [mailto:time-nuts-bounces@febo.com] On Behalf Of Charles Steinmetz
Sent: 24 October 2015 14:03
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Unified VCXO Carrier Board

Bruce wrote:

The MAX999 and ADCMP600 are the two comparator options noted on David's schematic.  Both parts suffer from a number of the design and die-level issues I noted in my previous message, and I have never obtained particularly good PN with either one.  Also, even the relatively direct path to the 10MHz output goes through two 'AC04 inverters and an 'AC541 line driver, which contribute additional PN.

Agreed.  Whether or not it is explicitly stated, I take "all circuitry to be enclosed and protected from drafts, and allowed to stabilize thermally before testing" as a given with any sensitive time or voltage circuit.

The spec sheet says both TimePod inputs accept -5 to +20dBm into 50 ohms.  -5dBm is less than 0.4Vp-p, which requires less than +/-4mA from the source, so a 0-5v comparator output feeding a coupling capacitor and a 560 ohm series resistor should work fine as long as the comparator can source and sink at least 4mA.

Alternatively, a 0-5v comparator output could be buffered with three
'AC04 inverters in parallel, or an 'AC line driver -- but that adds the PN of the gates.

It has just enough effect to correct the very small (<1%) asymmetry due to the unbalanced drive.  (With no resistor at Point A, the duty cycle is ~51%/49% high/low.)

According to the simulation, the resistor has no effect on the output amplitude until it is well below 1k ohms (at 1k ohm, the symmetry has been WAY overcompensated and the duty cycle is ~45%/55% high/low.

Best regards,

Charles

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On Sunday, October 25, 2015 09:21:02 AM Charles Steinmetz wrote:

Charles

There was no such suggestion, merely  a note that the amplitude was also
affected by this. This effect is important in that its probably advisable to
ensure that the input protection diodes of any gate being driven by the
output don't enter into conduction (I discovered that at least for the
74HC04 that the propagation delay jitter increased dramatically once the
input protection diodes began to conduct). Thus an increase in output
amplitude by a few hundred mV could be detrimental to the performance
of the driven logic device.

Whilst the symmetry adjustment effect is real its actually achieved by
adjusting the ratio of the emitter currents of the 2 transistors (its not a
threshold effect due to Vbe changes -they are too small but an adjustment
of the differential switching delays of the 2 transistors).
Consequently adjusting the ratio of emitter currents of Q1 and Q2 is best
made via a pot (200 ohm??) connected between the upper ends of R1 and
R2 (reduce R1 and R2 to 910 ohm) with its wiper connected to the C5, C6,
C7, R7 node.
Adjusting the wiper position has very little effect (tens of mV) on the
output amplitude whilst allowing adequate range of adjustment of the
output signal duty cycle.

Adjusting the value of R6 can be counter productive in that it spoils the
match to a 50 ohm load achieved via simple 2:1 (turns ratio) stepdown RF
transformer for the purposes of measuring the PN of the circuit.

Bruce

Am 24.10.2015 um 22:21 schrieb Bruce Griffiths:

For the sake of repeatability, could we agree on a common setup?
Timepod would be ok for me. Levels, sources, filters, splitters...

regards, Gerhard

I would be pleased to contribute a 100 MHz wenzel onyx for testing if
that'd be of value. I don't see myself getting to it anytime soon and this
project directly benefits almost half the things on my "never to do but
wish I could" list
On Sun, Oct 25, 2015 at 7:00 PM Bruce Griffiths bruce.griffiths@xtra.co.nz
wrote: