Full KE5FX evaluation of BG7TBL GPSDO here: http://www.ke5fx.com/gpscomp.htm

I'm wondering out loud if it might, like many hobbyist GPSDO's, be
frequency-locked rather than phase-locked and thus susceptible to
last-digit-counter bobble in some long-averaging counter.

Tim N3QE

On Wed, Aug 26, 2015 at 3:18 PM, Perry Sandeen via time-nuts <
time-nuts@febo.com> wrote:

Hi

Further investigation by list members in China came back with the information that this particular
design is indeed a FLL. The error is considered “acceptable” by the designer. This is not the case
on the various CDMA oriented GPSDO’s we typically play with in the US and Europe. All of those
designs (as far as I have seen) use PLL’s as their final lock stage.

Bob

So how does a frequency lock work?  How is it implemented? Can someone sketch a schematic?

And what equipment or technique is used to measure a 2hz error at 100GHz?

Bob

Look in the manual for the 8640B as they use FLL there when the lock button is pushed on the front panel. Simply, in one case, in lock, the numbers driving the frequency readout is saved and then when the oscillator drifts one way or the other, an EFC is applied that attempts to make the new readout driver number equal to the saved number. Regards - Mike

Mike B. Feher, EOZ Inc.
89 Arnold Blvd.
Howell, NJ, 07731
732-886-5960 office
908-902-3831 cell

-----Original Message-----
From: time-nuts [mailto:time-nuts-bounces@febo.com] On Behalf Of Bob Benward
Sent: Wednesday, August 26, 2015 11:55 PM
To: 'Discussion of precise time and frequency measurement'
Subject: Re: [time-nuts] Chinese GPSDO 10 MHz error

So how does a frequency lock work?  How is it implemented? Can someone sketch a schematic?

And what equipment or technique is used to measure a 2hz error at 100GHz?

Bob

time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.

Many hobbyist GPSDO's work, by counting OCXO cycles between some number of
GPS PPS assertions.

Software adjusts EFC based on frequency count. Often times the frequency
count used as input to the software has not just random +/- 1 bobble in
last digit, but also an extra count or two in last digit depending on the
hobbyists' gating choices. The systematic extra count or two will result in
a frequency offset between hobbyist GPSDO and PPS. Other times bugs in the
software that drives EFC might result in a systematic frequency offset.

We just had a poster last week who came here with such a scheme.

Tim N3QE

On Wed, Aug 26, 2015 at 11:54 PM, Bob Benward rbenward@verizon.net wrote:

The simplest form of a frequency locked loop is the XOR gate, when the
driving signals are 50% square waves. To achieve lock, the phase
difference will be proportional to the voltage needed to the VCO to
generate the desired frequency. Start with a 5V digital gate, suppose
your VCO needs 2.5V to be in frequency: the XOR output will be at 50%
duty cycle to generate, out of an RC, 2.5V and the phase difference
(between the reference and the VCO) will be 90 (or 270) degrees. The
difference will be more or less than 90 if the required voltage is
more or less than 2.5V (positive EFC) or will be more or less than 270
if the VCO has a negative EFC.

On Thu, Aug 27, 2015 at 5:54 AM, Bob Benward rbenward@verizon.net wrote:

On Thu, 27 Aug 2015 17:19:34 +0200
Azelio Boriani azelio.boriani@gmail.com wrote:

This is the description of a XOR gate based PLL, not an FLL.

The basic difference between PLL and FLL is very very simple:
A PLL measures phase, a FLL measures frequency.

The control loop then steers the measured value to be as close as
possible to a predetermined constant. As this steering loop is not
perfect, there will be a small error. Depending on what is measured,
it's either a phase or a frequency error.

		Attila Kinali

--
I must not become metastable.
Metastability is the mind-killer.
Metastability is the little-death that brings total obliteration.
I will face my metastability.
I will permit it to pass over me and through me.
And when it has gone past I will turn the inner eye to see its path.
Where the metastability has gone there will be nothing. Only I will remain.

it is a bit more complicated FLL need circuit which is sensitive to
frequency difference, it looks always,  PLL need a phase detector  and
has a capture range, which is depend mainly on the bandwidth of the loop
filter
there are combined phase /frequency detectors, which are sequential
circuits/logic, usually with some uncertainty --and therefore more phase
noise-- at zero phase difference
73

Alex

On 8/27/2015 1:50 PM, Attila Kinali wrote:

Hi

As with all things, this is a “that depends" sort of thing. You can measure it with a (accurate)
wall clock if you wait for 10^11 seconds (that’s quite a while). If you have a counter than
can measure 1x10^-9 s (1 ns) then you can get to 1x10^-11 by watching a pps for about a
hundred seconds. That’s not to bad to do. If you want to do it quickly, there are commercial
test boxes (the TimePod is one of many) that will measure much better than this at 1 second.
If you want do it in the basement, a DMTD is a cheap way to do it.

In all of these cases, you need something “better than” the device you are trying to measure to
use as a comparison standard. Put another way - your counter needs to be calibrated to better than 1 ppm
to measure 1 ppm. In the case of the GPSDO measurement, checking against a Cs standard or a
Hydrogen Maser would work. You might also use a “known good” GPSDO.

The comparison may be between 1 pps outputs or between 10 MHz outputs. In both cases the data
should be the same. Your choice of 1 pps or 10 MHz needs to match up between your measuring
gear, your DUT, and your reference standard.

Lots of choices, lots of ways to do it. Many pieces of gear you could use to get the job done.

Bob