Chinese GPSDO 10 MHz error
Since I have not found a strong definition for the FLL, I assumed: if
PLL= zero phase error (and so zero frequency error) the FLL= same
frequency, random phase. The XOR with RC is a perfect fit for this:
same frequency all the time but phase determined by the EFC needed to
have that frequency. The phase = constant, in the XOR/RC is true as
long as the VCO is stable and the EFC has not to be altered to steer
the VCO, that constant is not a design parameter but walks with the
VCO frequency movement.
On Thu, Aug 27, 2015 at 10:50 PM, Attila Kinali attila@kinali.ch wrote:
On Thu, 27 Aug 2015 17:19:34 +0200
Azelio Boriani azelio.boriani@gmail.com wrote:
The simplest form of a frequency locked loop is the XOR gate, when the
driving signals are 50% square waves. To achieve lock, the phase
difference will be proportional to the voltage needed to the VCO to
generate the desired frequency. Start with a 5V digital gate, suppose
your VCO needs 2.5V to be in frequency: the XOR output will be at 50%
duty cycle to generate, out of an RC, 2.5V and the phase difference
(between the reference and the VCO) will be 90 (or 270) degrees. The
difference will be more or less than 90 if the required voltage is
more or less than 2.5V (positive EFC) or will be more or less than 270
if the VCO has a negative EFC.
This is the description of a XOR gate based PLL, not an FLL.
The basic difference between PLL and FLL is very very simple:
A PLL measures phase, a FLL measures frequency.
The control loop then steers the measured value to be as close as
possible to a predetermined constant. As this steering loop is not
perfect, there will be a small error. Depending on what is measured,
it's either a phase or a frequency error.
Attila Kinali
--
I must not become metastable.
Metastability is the mind-killer.
Metastability is the little-death that brings total obliteration.
I will face my metastability.
I will permit it to pass over me and through me.
And when it has gone past I will turn the inner eye to see its path.
Where the metastability has gone there will be nothing. Only I will remain.
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Attila,
I concur with you, what Azelio described is a standard off the shelf PLL.
An XOR for a Type I phase discriminator, characterized by a 90 degree phase
lock, and with more complicated logic, a Type II PLL which locks at zero
degrees. In a well designed loop, in both cases over the long term the
frequency is exact, what it does have to a large extent, is phase jitter.
So how does someone measure an error to 2 parts in a hundred billion? Or is
that a 2 cycle slip in 100 gig cycles?
Thanks to all that replied.
Bob
-----Original Message-----
From: time-nuts [mailto:time-nuts-bounces@febo.com] On Behalf Of Attila
Kinali
Sent: Thursday, August 27, 2015 4:51 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Chinese GPSDO 10 MHz error
On Thu, 27 Aug 2015 17:19:34 +0200
Azelio Boriani azelio.boriani@gmail.com wrote:
The simplest form of a frequency locked loop is the XOR gate, when the
driving signals are 50% square waves. To achieve lock, the phase
difference will be proportional to the voltage needed to the VCO to
generate the desired frequency. Start with a 5V digital gate, suppose
your VCO needs 2.5V to be in frequency: the XOR output will be at 50%
duty cycle to generate, out of an RC, 2.5V and the phase difference
(between the reference and the VCO) will be 90 (or 270) degrees. The
difference will be more or less than 90 if the required voltage is
more or less than 2.5V (positive EFC) or will be more or less than 270
if the VCO has a negative EFC.
This is the description of a XOR gate based PLL, not an FLL.
The basic difference between PLL and FLL is very very simple:
A PLL measures phase, a FLL measures frequency.
The control loop then steers the measured value to be as close as
possible to
a predetermined constant. As this steering loop is not perfect, there
will be a
small error. Depending on what is measured, it's either a phase or a
frequency error.
Attila Kinali
--
I must not become metastable.
Metastability is the mind-killer.
Metastability is the little-death that brings total obliteration.
I will face my metastability.
I will permit it to pass over me and through me.
And when it has gone past I will turn the inner eye to see its path.
Where the metastability has gone there will be nothing. Only I will
remain.
time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Hi
At the most basic level:
FLL is frequency locked. Consider a lock system driven by an FM discriminator. (That’s
how the idea originally was done.) The output of the detector is a voltage proportional to the
frequency error. With a simple loop (gain only / no integrator) you have a static frequency
error. More gain gets you less frequency error.
PLL is a phase locked loop. A system with a DBM running as a detector is an old school
way to do this. The output of the detector is proportional to the phase difference. With a simple loop
(gain only, no integrator) you have a static phase error. More gain gets you less phase error
and possibly stability issues.
If you add an integrator to either control loop, things get more complicated. If you go further than that they
get you into a lot of debates :) The distinction between the two is much easier to see when each is paired
with a simple loop.
Bob
On Aug 27, 2015, at 7:36 PM, Azelio Boriani azelio.boriani@gmail.com wrote:
Since I have not found a strong definition for the FLL, I assumed: if
PLL= zero phase error (and so zero frequency error) the FLL= same
frequency, random phase. The XOR with RC is a perfect fit for this:
same frequency all the time but phase determined by the EFC needed to
have that frequency. The phase = constant, in the XOR/RC is true as
long as the VCO is stable and the EFC has not to be altered to steer
the VCO, that constant is not a design parameter but walks with the
VCO frequency movement.
On Thu, Aug 27, 2015 at 10:50 PM, Attila Kinali attila@kinali.ch wrote:
On Thu, 27 Aug 2015 17:19:34 +0200
Azelio Boriani azelio.boriani@gmail.com wrote:
The simplest form of a frequency locked loop is the XOR gate, when the
driving signals are 50% square waves. To achieve lock, the phase
difference will be proportional to the voltage needed to the VCO to
generate the desired frequency. Start with a 5V digital gate, suppose
your VCO needs 2.5V to be in frequency: the XOR output will be at 50%
duty cycle to generate, out of an RC, 2.5V and the phase difference
(between the reference and the VCO) will be 90 (or 270) degrees. The
difference will be more or less than 90 if the required voltage is
more or less than 2.5V (positive EFC) or will be more or less than 270
if the VCO has a negative EFC.
This is the description of a XOR gate based PLL, not an FLL.
The basic difference between PLL and FLL is very very simple:
A PLL measures phase, a FLL measures frequency.
The control loop then steers the measured value to be as close as
possible to a predetermined constant. As this steering loop is not
perfect, there will be a small error. Depending on what is measured,
it's either a phase or a frequency error.
Attila Kinali
--
I must not become metastable.
Metastability is the mind-killer.
Metastability is the little-death that brings total obliteration.
I will face my metastability.
I will permit it to pass over me and through me.
And when it has gone past I will turn the inner eye to see its path.
Where the metastability has gone there will be nothing. Only I will remain.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
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Hi
You can measure 2 cycles in at 100 GHz if you wish. Since these GPSDO’s only
put out 10 MHz, it would be a lot of work to multiply them up there. By far the more
practical approach is to measure the phase offset at 10 MHz and go from there.
If one cycle in 1 second is 1x10^-7 (10 MHz signals), then 1/10,000 of a cycle is going
to be 1x10^-11. There are a number of devices that can measure this (see my previous
post in this thread for more details).
Bob
On Aug 27, 2015, at 9:25 PM, Bob Benward rbenward@verizon.net wrote:
Attila,
I concur with you, what Azelio described is a standard off the shelf PLL.
An XOR for a Type I phase discriminator, characterized by a 90 degree phase
lock, and with more complicated logic, a Type II PLL which locks at zero
degrees. In a well designed loop, in both cases over the long term the
frequency is exact, what it does have to a large extent, is phase jitter.
So how does someone measure an error to 2 parts in a hundred billion? Or is
that a 2 cycle slip in 100 gig cycles?
Thanks to all that replied.
Bob
-----Original Message-----
From: time-nuts [mailto:time-nuts-bounces@febo.com] On Behalf Of Attila
Kinali
Sent: Thursday, August 27, 2015 4:51 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Chinese GPSDO 10 MHz error
On Thu, 27 Aug 2015 17:19:34 +0200
Azelio Boriani azelio.boriani@gmail.com wrote:
The simplest form of a frequency locked loop is the XOR gate, when the
driving signals are 50% square waves. To achieve lock, the phase
difference will be proportional to the voltage needed to the VCO to
generate the desired frequency. Start with a 5V digital gate, suppose
your VCO needs 2.5V to be in frequency: the XOR output will be at 50%
duty cycle to generate, out of an RC, 2.5V and the phase difference
(between the reference and the VCO) will be 90 (or 270) degrees. The
difference will be more or less than 90 if the required voltage is
more or less than 2.5V (positive EFC) or will be more or less than 270
if the VCO has a negative EFC.
This is the description of a XOR gate based PLL, not an FLL.
The basic difference between PLL and FLL is very very simple:
A PLL measures phase, a FLL measures frequency.
The control loop then steers the measured value to be as close as
possible to
a predetermined constant. As this steering loop is not perfect, there
will be a
small error. Depending on what is measured, it's either a phase or a
frequency error.
Attila Kinali
--
I must not become metastable.
Metastability is the mind-killer.
Metastability is the little-death that brings total obliteration.
I will face my metastability.
I will permit it to pass over me and through me.
And when it has gone past I will turn the inner eye to see its path.
Where the metastability has gone there will be nothing. Only I will
remain.
time-nuts mailing list -- time-nuts@febo.com To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.