Why do you want feedback for a DDS?

It's not a PLL with a bunch of analog parts that needs tweaking to get the
right output.  On a DDS, if you know the input clock, you can predict exactly
what will come out, spurs and all.

There is a layer of math associated with a DDS that I don't understand.

Suppose you have 10 MHz input clock and a 20 bit DDS.  If you want 1 KHz out,
your choices are 1001.359 and 991.822  (assuming I did the math right)

10 MHz to 1 KHz is a simple divide by 10000.  But a 20 bit DDS can't do that
cleanly.  On the other hand, if you use decimal arithmetic rather than
binary, you get 1 KHz exactly.

I think that can be generalized to dividing by any X rather than 2^N or 10^M.
So you can make an exact output for any Fin*P/Q where P << Q.

I think that gives you the same frequencies as a traditional PLL with
dividers on the input and feedback.  But you don't get to filter the analog
control voltage and you only get the frequencies where the divider on the
input frequency is bigger than the divider in the feedback path.

Back to the initial question:

Dropping out the multiply by 2998.01 and divide by 757
we want 3757 = 2271
we have 3732 = 2196
difference is 75
we have 61
difference is 14

So "about 55" is 2998.01*14 /757 or 55.445

I assume he can use whatever technology he used to get 297 MHz, just plug in
14 rather than 61.

Or run a 14/61 PLL from the 241.6 clock.

But I'm missing a couple of key ideas.

How does one build a PLL at 3 GHz or 9 GHz?

What does "exact" mean in this context?  Is that something to do with phase
noise, or does it just mean we can't round off the numbers?

Is there actually a 2998.01 clock?  If so, why is a simple 3x PLL not the
right answer?

Perhaps the true master clock is actually S-LO at 2998.01*732/757, and it's
just written that way to make all the ratios visible for reasons that are
important when you look at some other part of the problem.

--
These are my opinions, not necessarily my employer's.  I hate spam.

Hi Hal,

I guess you are right. A DDS where I place a sine table spanning
2^20=1048576 locations will allow me to generate fout=fin*(step/2^20) but if
I choose to use only 1000000 locations I can generate 1 kHz from 10 MHz
exactly. Therefore this system would not need feedback. I have not looked at
the details of how the DDS chips can be controlled, but there must be a way
to tell them not to use the full RAM. So I guess then it boils down to a
comparison between this DDS plus mixer based solution against Rick's
solution (which IMO answers your question on how one builds a PLL at those
frequencies).
Concerning your other questions:

• Yes, exact means we can't round off the numbers.
• Concerning precision, I think his 0.01 degree spec must apply to an RMS
  deviation measurement during a certain time (maybe the whole year run, or
  just some other unit of time meaningful to operators) between the real
  8994.03 MHz driving the beam (obviously not accessible to him) and his
  synthesized one. He will notice if things are wrong but looking at his beam
  measurements (made using his synthesized 8994.03 MHz).
• I don't think he has access to any other clocks aside from the ones he
  mentions.

So DDS vs. a good VCO. Any thoughts?

Javier

On Sun, Aug 16, 2009 at 2:25 AM, Hal Murray hmurray@megapathdsl.net wrote:

On 8/16/09 2:52 AM, "Javier Serrano" javier.serrano.pareja@gmail.com
wrote:

The usual DDS chips (e.g. From Analog Devices) have a built in table of
fixed length.  If you want to use something other than the power of 2 it
comes with, you'll need to implement the NCO in an FPGA, with an external
DAC.

Depending on what your spur requirements are, although, you're lucky because
you don't need tunability, you might want to look at doing one of the
various forms of error compensation.

Watch out for aliasing of the harmonics of the output back into band. No DAC
is perfect, so you get some (unpredictable from the data sheet) harmonic
distortion of the output waveform.

The application notes from Analog Devices cover all this sort of thing, and
there are off-the-shelf free LogicCores, etc., from most of the FPGA vendors
for the building blocks.

Javier Serrano wrote:

Most off the shelf DDS chips is for power-of-two only.

If you want any other modulus, you have to roll it yourself... i.e. FPGA.

Rich's proposal is very sound and similar to what I would consider. I
just haven't toyed with DROs but should get my wet feet some day... also
true for chip oscillators in that range.

Cheers,
Magnus

On 8/16/09 10:19 AM, "Magnus Danielson" magnus@rubidium.dyndns.org wrote:

There's a company up near Lake Tahoe (California) (I think that's where they
are) that does a tiny (<1cc) YIG oscillator that would be interesting to
fool with.

The challenge in making a high performance synthesizer is not so much the
actual VCO (whether it be DRO or MMIC or YIG or whatever) but getting the
microwave frequency down to where it can be compared with the reference. You
can do a straight divider, but then, the number of divide ratios is limited,
because fast dividers tend to be powers of two, or, at best, small integers.

You can then PLL that against the output of a DDS.  (this is what we did in
a breadboard at JPL, mostly to test out the parts, more than as an actual
design.. Hittite was developing (has developed by now) a GaAs MMIC PLL for
this kind of application (basically a xN PLL where N is smallish (<100)).
Some of their VCOs have an onchip divider too, which makes getting the
frequency down to where the programmable divider in the PLL chip can handle
it.

Or, you can use your quiet reference oscillator, and multiply that up to
somewhere near your microwave frequency, mix it with the microwave signal,
and use the output of the mixer as the input to your PLL phase/frequency
detector.

Or, you can use a sampling phase detector in your PLL (which requires a
hefty drive power, typically) driven by some DDS derived reference
frequency.  This is the traditional approach we (and others) have used in
deep space transponders in the past (without the DDS.. Driven by a carefully
hand tuned VCXO.. We did do a breadboard with the DDS approach, but we
couldn't get DRO tuning ranges over the whole 50-100 MHz we needed.)

Or, you can do a variety of mix and match schemes where you multiply a quiet
fixed frequency reference up, and mix that with some DDS derived output,
possibly itself multiplied up.

They all have different tradeoffs in terms of ultimate phase noise and
tuning ranges (and, of course, the usual issues of inloop and out of loop
noise contributions, etc.), as well as gain budgets, filtering requirements,
etc.

Lux, Jim (337C) wrote:

Analog Devices is working on a variable modulus DDS, that should
eliminate the need to roll your own with an FPGA.

Rick Karlquist N6RK

That would be very nifty.  They have a DDS (or at least a patent on one)
that uses CORDIC to generate the samples, rather than a table of sin/cos, so
that might be a good start.  I suppose it's a matter of trading silicon for
the lookup table for silicon for the complex multiplier.  And, I would think
they'd want to still have the table, so the user can control with a phase
increment, rather than cos(increment) and sin(increment).

On 8/16/09 11:33 AM, "Rick Karlquist" richard@karlquist.com wrote:

I designed a board awhile back to try out some of the off-the-shelf PLL
chips from the same manufacturer: http://www.ke5fx.com/hpll.htm .  It's not
in the league that's being discussed here (although the JPL folks will find
the attempt amusing).

I like the performance of Hittite's parts, but they sure are power-hungry,
and the QFN packages they use aren't easy to solder at home.  If you don't
need unusually high reference (Fcomp) frequencies, the Analog Devices CMOS
parts are preferable IMHO just because they're easier to play with.

These questions IMHO are exactly the right ones to ask, before speculating
on unconventional topologies and complicated block diagrams.  A birds'-eye
view of the overall conversion scheme would be helpful, assuming it's not
proprietary.

-- john, KE5FX

On 8/16/09 1:26 PM, "John Miles" jmiles@pop.net wrote:

Yours aren't all that much different than ours. (the link a few posts ago
has photos of our breadboard).  The main difference is that we get paid to
do it <grin>.

Oh yes they are!.  But, when you compare against other techniques, the "all
inclusive" power to do the synthesizer isn't all that different.  The DRO is
about the same power as the GaAs DRO. The GaAs divider is a huge power
sucker, but, in comparing to an older design using a sampling phase
detector, you have to figure in the huge power needed to hit the SPD with
it's +17dBm or +20dBm LO to make it work.  100mW linear amps tend not to be
very efficient.  (the SPD is basically a comb generator and mixer combined
in one, and to get enough drive into the "mixer" you have to have enough
power in the comb "teeth" to make it work.)

Yes, indeed.  There is a trade between high and low reference frequencies in
the PLL.  High means that the loop bandwidth can be wider (if you've got a
quiet reference), and N is smaller you've got a smaller 20log(N) increase in
the phase noise from the reference. On the other hand, you have to have a
quiet reference.  TANSTAAFL

You see that all the time, where you go through gyrations to locally
optimize because of a perception that the other parts of the system are cast
in concrete.

Hi, I've been meaning to post a proper bird's eye view since John requested
it. It just took me some time because I am not the source of this
information. I have first to identify the application: low level RF control.
In particle accelerators, charged particles are accelerated in RF cavities
and it is very important to control the RF field inside the cavities
according to some set points. In this accelerator there are 23 S-band
cavities and 1 X-band cavity. Here's the S-band controller:

There is down-conversion of the S-input coming from the cavity, down to a
reasonable frequency for FPGA processing, then up-conversion to generate a
S-band signal to send back to the cavity, closing the loop.
And here's the X-band system:

As you see, it's basically a wrapper around the S-band system, so as to
reuse as much as possible from it. The X signal is at a frequency four times
that of the S signal. That's why he needs a 3S, to use it in the
down-conversion and end up with 1S to feed to the S-input. The box with a
question mark in the diagram is the subject of this thread. The 241.6 MHz is
generated remotely, i.e. no access to 2998.01 MHz in the X-system. There is
an X-reference (4*S) around, so taking that and multiplying by 3/4 is an
option, but he'd rather not touch that reference if possible.
He will be doing active calibrations so long term drift (something that
occurs at 10 Hz or slower) should be taken care of. High frequency jitter
(>1 MHz) is also not a big issue since he can average it out from his
measurements. What stinks is the phase noise around 10 kHz. That's a
problem. All these by the way apply to departures of the field in the cavity
wrt the x-reference.
I hope this gives some context, it's the least I could do for such good
help. This is a fantastic list. Thanks everyone!

Javier

On Mon, Aug 17, 2009 at 3:20 AM, Lux, Jim (337C)
james.p.lux@jpl.nasa.govwrote:
....<snip>