Programmable clock for BFO use....noise
Rick said:
"The trouble with a DDS is that you need a microcontroller with software
just to baby sit the thing."
Yes, I know what you mean. I wouldn't want to go through all that. I'm
picturing more like the small, cheap DDS boards that show up on ebay.
Maybe the right stuff could be found that can stand alone, for maybe a
tenth the cost of a custom crystal or XO.
I've always been kind of frustrated with not being able to readily use
most of the cool new technologies in ICs, due to the SMT packaging, and
the need for programming them via serial ports. I have saved a number of
comparatively old-school, obsolete DDS and PLL devices, because they are
parallel controlled, and can be hard-wired for fixed or limited functions.
Also, speaking of PLLs, maybe that would be the way to go for the OP -
depending on the particular frequencies needed, and the resulting
complexity of the divider(s).
Ed
Not when I built them in the late 60's and early 70's. All discrete. 73 -
Mike
Mike B. Feher, N4FS
89 Arnold Blvd.
Howell NJ 07731
848-245-9115
-----Original Message-----
From: time-nuts time-nuts-bounces@lists.febo.com On Behalf Of Richard
(Rick) Karlquist
Sent: Friday, September 14, 2018 7:15 PM
To: Discussion of precise time and frequency measurement
time-nuts@lists.febo.com; ed breya eb@telight.com
Subject: Re: [time-nuts] Programmable clock for BFO use....noise
Finally, of course, you can use DDS. This is nearly an ideal case for
The trouble with a DDS is that you need a microcontroller with software just
to baby sit the thing.
Rick N6RK
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The beauty of a $2 arduino and a drop of code snitched from Engineer google.
OK enough of that back to the thread.
Regards
Paul
WB8TSL
On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher mfeher@eozinc.com wrote:
Not when I built them in the late 60's and early 70's. All discrete. 73 -
Mike
Mike B. Feher, N4FS
89 Arnold Blvd.
Howell NJ 07731
848-245-9115
-----Original Message-----
From: time-nuts time-nuts-bounces@lists.febo.com On Behalf Of Richard
(Rick) Karlquist
Sent: Friday, September 14, 2018 7:15 PM
To: Discussion of precise time and frequency measurement
time-nuts@lists.febo.com; ed breya eb@telight.com
Subject: Re: [time-nuts] Programmable clock for BFO use....noise
Finally, of course, you can use DDS. This is nearly an ideal case for
The trouble with a DDS is that you need a microcontroller with software
just
to baby sit the thing.
Rick N6RK
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Would a mems oscillator such as a dsc6183 possibly work for you? I'm
uncertain if the characteristics of a mems oscillator is compatible with
your application.
For odd frequencies I often head toward a mems oscillator since many can be
programmed to any reasonable frequency. For example one can buy dsc6183
blanks and use a programmer to program it to your desired frequency.
The dsc61xx series happens to be one time programmable so you only get one
shot at it per blank. The programmer is relatively inexpensive, but might
be more than one would want to pay for a one off. I have found that having
a collection of blanks and a programmer is very useful since it allows me
to generate any frequency oscillator I need.
There are other mems oscillator models out there, with various specs and
programming (or not) options.
On Fri, Sep 14, 2018, 11:16 AM lstoskopf@cox.net wrote:
Off topic for this list, but you guys are experts in oscillator noise!
Playing with some mechanical filters. Need USB and LSB crystals for the
BFO. No one seems to make crystals anymore, especially in the 253 KHz
range!
Looking at the DigiKey Cardinal programmable oscillators. Cheap and
available: CPPC1LZ A5B6
Anyone have an idea how noisy these would be after a division by 4 to get
them in range?
Thanks,
N0UU
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Got a whole bunch of answers all with useful info. I think I will go with Hans' 4 output board to see if the project works at all and go from there. Off on a three week tour of Italy to Malta and should have the parts when I get back. This is one of those weird design things so maybe the oscillators won't be the problem!
N0UU
Somebody send me the URL to that board thank you
On Fri, Sep 14, 2018, 9:21 PM lstoskopf@cox.net wrote:
Got a whole bunch of answers all with useful info. I think I will go
with Hans' 4 output board to see if the project works at all and go from
there. Off on a three week tour of Italy to Malta and should have the
parts when I get back. This is one of those weird design things so maybe
the oscillators won't be the problem!
N0UU
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Depending on the cost of those mems devices, a microcontroller can be so
trivial that you can just consider it as a smart eprom. Like Tom's PICDIV
dividers, which act more like perfect-for-pupose division chip than a micro.
On Sat, Sep 15, 2018 at 4:31 AM, Forrest Christian (List Account) <
lists@packetflux.com> wrote:
Would a mems oscillator such as a dsc6183 possibly work for you? I'm
uncertain if the characteristics of a mems oscillator is compatible with
your application.
For odd frequencies I often head toward a mems oscillator since many can be
programmed to any reasonable frequency. For example one can buy dsc6183
blanks and use a programmer to program it to your desired frequency.
The dsc61xx series happens to be one time programmable so you only get one
shot at it per blank. The programmer is relatively inexpensive, but might
be more than one would want to pay for a one off. I have found that having
a collection of blanks and a programmer is very useful since it allows me
to generate any frequency oscillator I need.
There are other mems oscillator models out there, with various specs and
programming (or not) options.
On Fri, Sep 14, 2018, 11:16 AM lstoskopf@cox.net wrote:
Off topic for this list, but you guys are experts in oscillator noise!
Playing with some mechanical filters. Need USB and LSB crystals for the
BFO. No one seems to make crystals anymore, especially in the 253 KHz
range!
Looking at the DigiKey Cardinal programmable oscillators. Cheap and
available: CPPC1LZ A5B6
Anyone have an idea how noisy these would be after a division by 4 to get
them in range?
Thanks,
N0UU
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On Fri, 14 Sep 2018 21:42:05 +0000
Bryan _ bpl521@outlook.com wrote:
I would be interested in hearing more of the more suitable classes of
logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz
Any logic family works, as long as it is fast enough to handle your
input frequency. Due to the non-linear (aka digital) behaviour
of a D-Flipflop style divider, it is recommended to use the slowest
possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
mentioned).
As a rule of thumb, I'd say that the FF should not be more than 10 to 20
times faster than the input frequency, to limit noise down-mixing.
If your FF is too fast or you want to reduce the noise floor, capacitively
loading and/or having some additional resistance in the Vcc and GND lines
will help slow it down. But ensure that the resistance is still low enough
that the FF's supply stays within specs at all time. Similarly, the
capacitive loading should be low enough that the output current is within
reasonable bounds.
Alternatively, using the Λ-divider approach[2] and introducing voltage
steps between 0 and 1 will also reduce down-mixing.
If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.
Attila Kinali
[1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990
[2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
by Calosso and Rubiola 2013
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.
Good points, Ulrich Rohde
Sent from my iPhone
On Sep 15, 2018, at 6:26 AM, Attila Kinali attila@kinali.ch wrote:
On Fri, 14 Sep 2018 21:42:05 +0000
Bryan _ bpl521@outlook.com wrote:
I would be interested in hearing more of the more suitable classes of
logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz
Any logic family works, as long as it is fast enough to handle your
input frequency. Due to the non-linear (aka digital) behaviour
of a D-Flipflop style divider, it is recommended to use the slowest
possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
mentioned).
As a rule of thumb, I'd say that the FF should not be more than 10 to 20
times faster than the input frequency, to limit noise down-mixing.
If your FF is too fast or you want to reduce the noise floor, capacitively
loading and/or having some additional resistance in the Vcc and GND lines
will help slow it down. But ensure that the resistance is still low enough
that the FF's supply stays within specs at all time. Similarly, the
capacitive loading should be low enough that the output current is within
reasonable bounds.
Alternatively, using the Λ-divider approach[2] and introducing voltage
steps between 0 and 1 will also reduce down-mixing.
If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.
Attila Kinali
[1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990
[2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
by Calosso and Rubiola 2013
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.
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Hi Attila,
Very interesting, thanks.
I found ref (2) by seems that need to pay or be to registered as a researcher to get ref (1).
Is there a easier way to get a copy ?
Thx,
Gilles.
Le 15 sept. 2018 à 12:26, Attila Kinali attila@kinali.ch a écrit :
On Fri, 14 Sep 2018 21:42:05 +0000
Bryan _ bpl521@outlook.com wrote:
I would be interested in hearing more of the more suitable classes of
logic chips. I have a 20Mhz rubidium that I wanted to divide down to 10Mhz
Any logic family works, as long as it is fast enough to handle your
input frequency. Due to the non-linear (aka digital) behaviour
of a D-Flipflop style divider, it is recommended to use the slowest
possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
mentioned).
As a rule of thumb, I'd say that the FF should not be more than 10 to 20
times faster than the input frequency, to limit noise down-mixing.
If your FF is too fast or you want to reduce the noise floor, capacitively
loading and/or having some additional resistance in the Vcc and GND lines
will help slow it down. But ensure that the resistance is still low enough
that the FF's supply stays within specs at all time. Similarly, the
capacitive loading should be low enough that the output current is within
reasonable bounds.
Alternatively, using the Λ-divider approach[2] and introducing voltage
steps between 0 and 1 will also reduce down-mixing.
If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.
Attila Kinali
[1] "Modeling Phase Noise in Frequency Dividers," by Egan, 1990
[2] "The Sampling Theorem in Pi and Lambda Digital Frequency Dividers,"
by Calosso and Rubiola 2013
--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.
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