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AK

Attila Kinali

Sat, Sep 15, 2018 12:29 PM

On Sat, 15 Sep 2018 13:13:40 +0200
Club-Internet Clemgill clemgill@club-internet.fr wrote:

Very interesting, thanks.
I found ref (2) by seems that need to pay or be to registered as a researcher to get ref (1).
Is there a easier way to get a copy ?

Yes, use sci-hub: https://sci-hub.tw/10.1109/58.56498

		Attila Kinali

--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

On Sat, 15 Sep 2018 13:13:40 +0200 Club-Internet Clemgill <clemgill@club-internet.fr> wrote: > Very interesting, thanks. > I found ref (2) by seems that need to pay or be to registered as a researcher to get ref (1). > Is there a easier way to get a copy ? Yes, use sci-hub: https://sci-hub.tw/10.1109/58.56498 Attila Kinali -- <JaberWorky> The bad part of Zurich is where the degenerates throw DARK chocolate at you.

R(

Richard (Rick) Karlquist

Sat, Sep 15, 2018 3:38 PM

Another great posting from Attila that keeps the S/N ratio
on this list high.

On 9/15/2018 3:26 AM, Attila Kinali wrote:

possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
mentioned).

Wow, I never knew this in 45 years of designing synthesizers!
I do remember that some of the frequency counter engineers at HP
talked about noise aliasing. I think this is another way of
describing the same problem.

About 10 years ago, the frequency synthesizer chip vendors started
talking about a Figure of Merit (FOM) that predicted phase noise floor,
and it also included the 10 LOG N noise scaling. An application
engineer at ADI told me this was a characteristic of the sampling phase
detector that all these chips used. But I always wondered if the
frequency divider could come into play. The way FOM is defined,
it doesn't distinguish between phase detector and divider noise.

At Agilent, we used to make a lot of lab demos using a Centellax
(now Microsemi AKA Microchip) frequency divider that could divide by any
number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
to divide down to 50 MHz. Now you have explained it.

If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle. Otherwise
flicker noise which has been up-mixed by a previous stage, will be down-mixed
into the signal band, increasing the close-in phase-noise.

Wow, another thing I never knew. The conventional wisdom was to
divide by any number (even or odd) and then follow that divider
with a divide by 2 flip flop to get 50%. Now, that is in question.
The now correct answer is to us a variable modulus prescaler to
divide by P and P+1, controlled by a toggle flip flop to make
half the divisions at P and half at P+1.

Does anyone else have experience with these issues?

Rick N6RK

Another great posting from Attila that keeps the S/N ratio on this list high. On 9/15/2018 3:26 AM, Attila Kinali wrote: > possible logic family for the task. Otherwise the harmonics of the > switching of the FF will down-mix high frequency white noise down > to the signal band (this is the reason for the 10*log(N) noise scaling > of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others > mentioned). Wow, I never knew this in 45 years of designing synthesizers! I do remember that some of the frequency counter engineers at HP talked about noise aliasing. I think this is another way of describing the same problem. About 10 years ago, the frequency synthesizer chip vendors started talking about a Figure of Merit (FOM) that predicted phase noise floor, and it also included the 10 LOG N noise scaling. An application engineer at ADI told me this was a characteristic of the sampling phase detector that all these chips used. But I always wondered if the frequency divider could come into play. The way FOM is defined, it doesn't distinguish between phase detector and divider noise. At Agilent, we used to make a lot of lab demos using a Centellax (now Microsemi AKA Microchip) frequency divider that could divide by any number between 8 and 511 up to 10 GHz. It was absolutely fabulous for dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried to divide down to 50 MHz. Now you have explained it. > > If you divide by something that is not a power of 2, then it is important > that each stage produces an output waveform with a 50% duty cycle. Otherwise > flicker noise which has been up-mixed by a previous stage, will be down-mixed > into the signal band, increasing the close-in phase-noise. Wow, another thing I never knew. The conventional wisdom was to divide by any number (even or odd) and then follow that divider with a divide by 2 flip flop to get 50%. Now, that is in question. The now correct answer is to us a variable modulus prescaler to divide by P and P+1, controlled by a toggle flip flop to make half the divisions at P and half at P+1. Does anyone else have experience with these issues? Rick N6RK

SS

Scott Stobbe

Sun, Sep 16, 2018 2:05 AM

That is fascinating. So, the 1PPS line on a GPSDO (a divide by 10Meg in
many cases) is 70 dB worse than the traditional 20log(N) PN scaling?

On Sat, Sep 15, 2018 at 11:40 AM Richard (Rick) Karlquist <
richard@karlquist.com> wrote:

Another great posting from Attila that keeps the S/N ratio
on this list high.

On 9/15/2018 3:26 AM, Attila Kinali wrote:

possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
mentioned).

Wow, I never knew this in 45 years of designing synthesizers!
I do remember that some of the frequency counter engineers at HP
talked about noise aliasing. I think this is another way of
describing the same problem.

About 10 years ago, the frequency synthesizer chip vendors started
talking about a Figure of Merit (FOM) that predicted phase noise floor,
and it also included the 10 LOG N noise scaling. An application
engineer at ADI told me this was a characteristic of the sampling phase
detector that all these chips used. But I always wondered if the
frequency divider could come into play. The way FOM is defined,
it doesn't distinguish between phase detector and divider noise.

At Agilent, we used to make a lot of lab demos using a Centellax
(now Microsemi AKA Microchip) frequency divider that could divide by any
number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
to divide down to 50 MHz. Now you have explained it.

If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle.

Otherwise

flicker noise which has been up-mixed by a previous stage, will be

down-mixed

into the signal band, increasing the close-in phase-noise.

Wow, another thing I never knew. The conventional wisdom was to
divide by any number (even or odd) and then follow that divider
with a divide by 2 flip flop to get 50%. Now, that is in question.
The now correct answer is to us a variable modulus prescaler to
divide by P and P+1, controlled by a toggle flip flop to make
half the divisions at P and half at P+1.

Does anyone else have experience with these issues?

Rick N6RK

time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to
http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.

That is fascinating. So, the 1PPS line on a GPSDO (a divide by 10Meg in many cases) is 70 dB worse than the traditional 20log(N) PN scaling? On Sat, Sep 15, 2018 at 11:40 AM Richard (Rick) Karlquist < richard@karlquist.com> wrote: > Another great posting from Attila that keeps the S/N ratio > on this list high. > > On 9/15/2018 3:26 AM, Attila Kinali wrote: > > > possible logic family for the task. Otherwise the harmonics of the > > switching of the FF will down-mix high frequency white noise down > > to the signal band (this is the reason for the 10*log(N) noise scaling > > of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others > > mentioned). > > Wow, I never knew this in 45 years of designing synthesizers! > I do remember that some of the frequency counter engineers at HP > talked about noise aliasing. I think this is another way of > describing the same problem. > > About 10 years ago, the frequency synthesizer chip vendors started > talking about a Figure of Merit (FOM) that predicted phase noise floor, > and it also included the 10 LOG N noise scaling. An application > engineer at ADI told me this was a characteristic of the sampling phase > detector that all these chips used. But I always wondered if the > frequency divider could come into play. The way FOM is defined, > it doesn't distinguish between phase detector and divider noise. > > At Agilent, we used to make a lot of lab demos using a Centellax > (now Microsemi AKA Microchip) frequency divider that could divide by any > number between 8 and 511 up to 10 GHz. It was absolutely fabulous for > dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried > to divide down to 50 MHz. Now you have explained it. > > > > If you divide by something that is not a power of 2, then it is important > > that each stage produces an output waveform with a 50% duty cycle. > Otherwise > > flicker noise which has been up-mixed by a previous stage, will be > down-mixed > > into the signal band, increasing the close-in phase-noise. > > Wow, another thing I never knew. The conventional wisdom was to > divide by any number (even or odd) and then follow that divider > with a divide by 2 flip flop to get 50%. Now, that is in question. > The now correct answer is to us a variable modulus prescaler to > divide by P and P+1, controlled by a toggle flip flop to make > half the divisions at P and half at P+1. > > Does anyone else have experience with these issues? > > Rick N6RK > > > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. >

BK

Bob kb8tq

Sun, Sep 16, 2018 2:57 AM

Hi

Most of the traditional rules about phase noise apply out to 10 or 20% of the “carrier”
frequency. If the carrier is 1Hz, then you are talking about the traditional definitions holding
out to 0.1 or 0.2 Hz relative to carrier. That’s deep in the 1/F noise part of the divider’s
“noise curve”.

Since the ADEV of the 1 PPS is typically no worse than the ADEV of the 10 MHz, it would be
hard to come up with a model where the 1 PPS has picked up a lot of extra noise.

Bob

On Sep 15, 2018, at 9:05 PM, Scott Stobbe scott.j.stobbe@gmail.com wrote:

That is fascinating. So, the 1PPS line on a GPSDO (a divide by 10Meg in
many cases) is 70 dB worse than the traditional 20log(N) PN scaling?

On Sat, Sep 15, 2018 at 11:40 AM Richard (Rick) Karlquist <
richard@karlquist.com> wrote:

Another great posting from Attila that keeps the S/N ratio
on this list high.

On 9/15/2018 3:26 AM, Attila Kinali wrote:

possible logic family for the task. Otherwise the harmonics of the
switching of the FF will down-mix high frequency white noise down
to the signal band (this is the reason for the 10*log(N) noise scaling
of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others
mentioned).

Wow, I never knew this in 45 years of designing synthesizers!
I do remember that some of the frequency counter engineers at HP
talked about noise aliasing. I think this is another way of
describing the same problem.

About 10 years ago, the frequency synthesizer chip vendors started
talking about a Figure of Merit (FOM) that predicted phase noise floor,
and it also included the 10 LOG N noise scaling. An application
engineer at ADI told me this was a characteristic of the sampling phase
detector that all these chips used. But I always wondered if the
frequency divider could come into play. The way FOM is defined,
it doesn't distinguish between phase detector and divider noise.

At Agilent, we used to make a lot of lab demos using a Centellax
(now Microsemi AKA Microchip) frequency divider that could divide by any
number between 8 and 511 up to 10 GHz. It was absolutely fabulous for
dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried
to divide down to 50 MHz. Now you have explained it.

If you divide by something that is not a power of 2, then it is important
that each stage produces an output waveform with a 50% duty cycle.

Otherwise

flicker noise which has been up-mixed by a previous stage, will be

down-mixed

into the signal band, increasing the close-in phase-noise.

Wow, another thing I never knew. The conventional wisdom was to
divide by any number (even or odd) and then follow that divider
with a divide by 2 flip flop to get 50%. Now, that is in question.
The now correct answer is to us a variable modulus prescaler to
divide by P and P+1, controlled by a toggle flip flop to make
half the divisions at P and half at P+1.

Does anyone else have experience with these issues?

Rick N6RK

time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to
http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.

time-nuts mailing list -- time-nuts@lists.febo.com
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and follow the instructions there.

Hi Most of the traditional rules about phase noise apply out to 10 or 20% of the “carrier” frequency. If the carrier is 1Hz, then you are talking about the traditional definitions holding out to 0.1 or 0.2 Hz relative to carrier. That’s *deep* in the 1/F noise part of the divider’s “noise curve”. Since the ADEV of the 1 PPS is typically no worse than the ADEV of the 10 MHz, it would be hard to come up with a model where the 1 PPS has picked up a lot of extra noise. Bob > On Sep 15, 2018, at 9:05 PM, Scott Stobbe <scott.j.stobbe@gmail.com> wrote: > > That is fascinating. So, the 1PPS line on a GPSDO (a divide by 10Meg in > many cases) is 70 dB worse than the traditional 20log(N) PN scaling? > > On Sat, Sep 15, 2018 at 11:40 AM Richard (Rick) Karlquist < > richard@karlquist.com> wrote: > >> Another great posting from Attila that keeps the S/N ratio >> on this list high. >> >> On 9/15/2018 3:26 AM, Attila Kinali wrote: >> >>> possible logic family for the task. Otherwise the harmonics of the >>> switching of the FF will down-mix high frequency white noise down >>> to the signal band (this is the reason for the 10*log(N) noise scaling >>> of digital divider that Egan[1] and Calosso/Rubiola[2] and a few others >>> mentioned). >> >> Wow, I never knew this in 45 years of designing synthesizers! >> I do remember that some of the frequency counter engineers at HP >> talked about noise aliasing. I think this is another way of >> describing the same problem. >> >> About 10 years ago, the frequency synthesizer chip vendors started >> talking about a Figure of Merit (FOM) that predicted phase noise floor, >> and it also included the 10 LOG N noise scaling. An application >> engineer at ADI told me this was a characteristic of the sampling phase >> detector that all these chips used. But I always wondered if the >> frequency divider could come into play. The way FOM is defined, >> it doesn't distinguish between phase detector and divider noise. >> >> At Agilent, we used to make a lot of lab demos using a Centellax >> (now Microsemi AKA Microchip) frequency divider that could divide by any >> number between 8 and 511 up to 10 GHz. It was absolutely fabulous for >> dividing 10 GHz down to 2.5 GHz. But 20 LOG N quit working if I tried >> to divide down to 50 MHz. Now you have explained it. >>> >>> If you divide by something that is not a power of 2, then it is important >>> that each stage produces an output waveform with a 50% duty cycle. >> Otherwise >>> flicker noise which has been up-mixed by a previous stage, will be >> down-mixed >>> into the signal band, increasing the close-in phase-noise. >> >> Wow, another thing I never knew. The conventional wisdom was to >> divide by any number (even or odd) and then follow that divider >> with a divide by 2 flip flop to get 50%. Now, that is in question. >> The now correct answer is to us a variable modulus prescaler to >> divide by P and P+1, controlled by a toggle flip flop to make >> half the divisions at P and half at P+1. >> >> Does anyone else have experience with these issues? >> >> Rick N6RK >> >> >> _______________________________________________ >> time-nuts mailing list -- time-nuts@lists.febo.com >> To unsubscribe, go to >> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com >> and follow the instructions there. >> > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there.

DJ

Didier Juges

Sun, Sep 16, 2018 12:49 PM

Not the same part number but probably similar in terms of performance:

http://www.ko4bb.com/getsimple/index.php?id=microprocessor-crystal-oscillator-comparison

Bottom line: use a true crystal oscillator, or make your own PLL, not a
programmable "microprocessor crystal"

On Fri, Sep 14, 2018, 11:15 AM lstoskopf@cox.net wrote:

Off topic for this list, but you guys are experts in oscillator noise!

Playing with some mechanical filters. Need USB and LSB crystals for the
BFO. No one seems to make crystals anymore, especially in the 253 KHz
range!

Looking at the DigiKey Cardinal programmable oscillators. Cheap and
available: CPPC1LZ A5B6

Anyone have an idea how noisy these would be after a division by 4 to get
them in range?

Thanks,

N0UU

time-nuts mailing list -- time-nuts@lists.febo.com
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Not the same part number but probably similar in terms of performance: http://www.ko4bb.com/getsimple/index.php?id=microprocessor-crystal-oscillator-comparison Bottom line: use a true crystal oscillator, or make your own PLL, not a programmable "microprocessor crystal" On Fri, Sep 14, 2018, 11:15 AM <lstoskopf@cox.net> wrote: > Off topic for this list, but you guys are experts in oscillator noise! > > Playing with some mechanical filters. Need USB and LSB crystals for the > BFO. No one seems to make crystals anymore, especially in the 253 KHz > range! > > Looking at the DigiKey Cardinal programmable oscillators. Cheap and > available: CPPC1LZ A5B6 > > Anyone have an idea how noisy these would be after a division by 4 to get > them in range? > > Thanks, > > N0UU > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to > http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. >

BK

Bob kb8tq

Sun, Sep 16, 2018 3:48 PM

Hi

Coming back to the basics of the design:

If you are playing with a normal radio, a BFO that drifts under a few Hertz is
going to be pretty much un-noticable. Drift is a bit of an elastic term in this case
since it can cover a bunch of different parameters on an oscillator (temperature
as things warm up / aging / retrace / voltage stability ….).

For fun, lets say that 25.3 Hz over a day and 5C is “adequate” for the task. Oddly
enough this makes the math easy. 25.3 Hz / 253 KHz = 1 / 10,000 = 100 ppm.

A crystal that drifts 1 ppm / C is not a super duper part at room temperature. Over
our 5C range, that’s only 5 ppm. It would have to be 10X worse to really eat into
our budget.

Aging / warmup / retrace wise, a crystal that moves a couple ppm in the first day
is moving a lot. Again not a big hit to our budget.

Voltage stability on a properly designed circuit with a normal voltage regulator should
be very small compared to the budget. Maybe it’s a ppm, probably less.

Bottom line - the crystal likely is doing >10X better than what our arbitrary spec would
require. That’s why a lot of radios do just fine with an L/C based BFO.

For even more fun, take a look at the likely drift of the mechanical filters involved. They
are not going to be as stable as the crystal ….. Even a crystal filter at 250KHz isn’t
going to be as stable as the AT cut based evaluation above.

Bob

On Sep 16, 2018, at 7:49 AM, Didier Juges shalimr9@gmail.com wrote:

Not the same part number but probably similar in terms of performance:

http://www.ko4bb.com/getsimple/index.php?id=microprocessor-crystal-oscillator-comparison

Bottom line: use a true crystal oscillator, or make your own PLL, not a
programmable "microprocessor crystal"

On Fri, Sep 14, 2018, 11:15 AM lstoskopf@cox.net wrote:

Off topic for this list, but you guys are experts in oscillator noise!

Playing with some mechanical filters. Need USB and LSB crystals for the
BFO. No one seems to make crystals anymore, especially in the 253 KHz
range!

Looking at the DigiKey Cardinal programmable oscillators. Cheap and
available: CPPC1LZ A5B6

Anyone have an idea how noisy these would be after a division by 4 to get
them in range?

Thanks,

N0UU

time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to
http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.

time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.

Hi Coming back to the basics of the design: If you are playing with a normal radio, a BFO that drifts under a few Hertz is going to be pretty much un-noticable. Drift is a bit of an elastic term in this case since it can cover a bunch of different parameters on an oscillator (temperature as things warm up / aging / retrace / voltage stability ….). For fun, lets say that 25.3 Hz over a day and 5C is “adequate” for the task. Oddly enough this makes the math easy. 25.3 Hz / 253 KHz = 1 / 10,000 = 100 ppm. A crystal that drifts 1 ppm / C is not a super duper part at room temperature. Over our 5C range, that’s only 5 ppm. It would have to be 10X worse to really eat into our budget. Aging / warmup / retrace wise, a crystal that moves a couple ppm in the first day is moving a lot. Again not a big hit to our budget. Voltage stability on a properly designed circuit with a normal voltage regulator should be very small compared to the budget. Maybe it’s a ppm, probably less. Bottom line - the crystal likely is doing >10X better than what our arbitrary spec would require. That’s why a lot of radios do just fine with an L/C based BFO. For even more fun, take a look at the likely drift of the mechanical filters involved. They are not going to be as stable as the crystal ….. Even a crystal filter at 250KHz isn’t going to be as stable as the AT cut based evaluation above. Bob > On Sep 16, 2018, at 7:49 AM, Didier Juges <shalimr9@gmail.com> wrote: > > Not the same part number but probably similar in terms of performance: > > http://www.ko4bb.com/getsimple/index.php?id=microprocessor-crystal-oscillator-comparison > > Bottom line: use a true crystal oscillator, or make your own PLL, not a > programmable "microprocessor crystal" > > On Fri, Sep 14, 2018, 11:15 AM <lstoskopf@cox.net> wrote: > >> Off topic for this list, but you guys are experts in oscillator noise! >> >> Playing with some mechanical filters. Need USB and LSB crystals for the >> BFO. No one seems to make crystals anymore, especially in the 253 KHz >> range! >> >> Looking at the DigiKey Cardinal programmable oscillators. Cheap and >> available: CPPC1LZ A5B6 >> >> Anyone have an idea how noisy these would be after a division by 4 to get >> them in range? >> >> Thanks, >> >> N0UU >> _______________________________________________ >> time-nuts mailing list -- time-nuts@lists.febo.com >> To unsubscribe, go to >> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com >> and follow the instructions there. >> > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there.

CW

Chris Waldrup

Sun, Sep 16, 2018 5:22 PM

How about using a ProgRock on Hans Summers QRP Labs website? This is a programmable crystal replacement.

Chris
KD4PBJ

On Sep 14, 2018, at 8:06 PM, paul swed paulswedb@gmail.com wrote:

The beauty of a $2 arduino and a drop of code snitched from Engineer google.
OK enough of that back to the thread.
Regards
Paul
WB8TSL

On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher mfeher@eozinc.com wrote:

Not when I built them in the late 60's and early 70's. All discrete. 73 -
Mike

Mike B. Feher, N4FS

89 Arnold Blvd.

Howell NJ 07731

848-245-9115

-----Original Message-----
From: time-nuts time-nuts-bounces@lists.febo.com On Behalf Of Richard
(Rick) Karlquist
Sent: Friday, September 14, 2018 7:15 PM
To: Discussion of precise time and frequency measurement
time-nuts@lists.febo.com; ed breya eb@telight.com
Subject: Re: [time-nuts] Programmable clock for BFO use....noise

Finally, of course, you can use DDS. This is nearly an ideal case for

The trouble with a DDS is that you need a microcontroller with software
just
to baby sit the thing.

Rick N6RK

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How about using a ProgRock on Hans Summers QRP Labs website? This is a programmable crystal replacement. Chris KD4PBJ > On Sep 14, 2018, at 8:06 PM, paul swed <paulswedb@gmail.com> wrote: > > The beauty of a $2 arduino and a drop of code snitched from Engineer google. > OK enough of that back to the thread. > Regards > Paul > WB8TSL > >> On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher <mfeher@eozinc.com> wrote: >> >> Not when I built them in the late 60's and early 70's. All discrete. 73 - >> Mike >> >> >> >> Mike B. Feher, N4FS >> >> 89 Arnold Blvd. >> >> Howell NJ 07731 >> >> 848-245-9115 >> >> >> >> -----Original Message----- >> From: time-nuts <time-nuts-bounces@lists.febo.com> On Behalf Of Richard >> (Rick) Karlquist >> Sent: Friday, September 14, 2018 7:15 PM >> To: Discussion of precise time and frequency measurement >> <time-nuts@lists.febo.com>; ed breya <eb@telight.com> >> Subject: Re: [time-nuts] Programmable clock for BFO use....noise >> >> >> >> >>> Finally, of course, you can use DDS. This is nearly an ideal case for >> >> >> >> The trouble with a DDS is that you need a microcontroller with software >> just >> to baby sit the thing. >> >> >> >> Rick N6RK >> >> >> >> _______________________________________________ >> >> time-nuts mailing list -- <mailto:time-nuts@lists.febo.com> >> time-nuts@lists.febo.com To unsubscribe, go to >> <http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com> >> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com >> >> and follow the instructions there. >> >> _______________________________________________ >> time-nuts mailing list -- time-nuts@lists.febo.com >> To unsubscribe, go to http://lists.febo.com/mailman/ >> listinfo/time-nuts_lists.febo.com >> and follow the instructions there. > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there.

MG

Mark Goldberg

Sun, Sep 16, 2018 6:00 PM

For a radio BFO you want something with low phase noise (low jitter). The
SI5351 is not designed for that, and it's jitter spec is 70 ps, which is
pretty noisy. It even has a spread spectrum mode that would be even worse.
They do have other parts designed for low jitter (< 1ps). Leo Bodnar's
GPSDOs with variable output clock frequencies are based on those chips and
they provide low phase noise, certainly enough for a radio.

Regards,

Mark

On Sun, Sep 16, 2018 at 10:22 AM, Chris Waldrup kd4pbj@gmail.com wrote:

How about using a ProgRock on Hans Summers QRP Labs website? This is a
programmable crystal replacement.

Chris
KD4PBJ

On Sep 14, 2018, at 8:06 PM, paul swed paulswedb@gmail.com wrote:

The beauty of a $2 arduino and a drop of code snitched from Engineer

google.

OK enough of that back to the thread.
Regards
Paul
WB8TSL

On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher mfeher@eozinc.com wrote:

Not when I built them in the late 60's and early 70's. All discrete. 73

Mike

Mike B. Feher, N4FS

89 Arnold Blvd.

Howell NJ 07731

848-245-9115

-----Original Message-----
From: time-nuts time-nuts-bounces@lists.febo.com On Behalf Of Richard
(Rick) Karlquist
Sent: Friday, September 14, 2018 7:15 PM
To: Discussion of precise time and frequency measurement
time-nuts@lists.febo.com; ed breya eb@telight.com
Subject: Re: [time-nuts] Programmable clock for BFO use....noise

Finally, of course, you can use DDS. This is nearly an ideal case for

The trouble with a DDS is that you need a microcontroller with software
just
to baby sit the thing.

Rick N6RK

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For a radio BFO you want something with low phase noise (low jitter). The SI5351 is not designed for that, and it's jitter spec is 70 ps, which is pretty noisy. It even has a spread spectrum mode that would be even worse. They do have other parts designed for low jitter (< 1ps). Leo Bodnar's GPSDOs with variable output clock frequencies are based on those chips and they provide low phase noise, certainly enough for a radio. Regards, Mark On Sun, Sep 16, 2018 at 10:22 AM, Chris Waldrup <kd4pbj@gmail.com> wrote: > How about using a ProgRock on Hans Summers QRP Labs website? This is a > programmable crystal replacement. > > Chris > KD4PBJ > > > On Sep 14, 2018, at 8:06 PM, paul swed <paulswedb@gmail.com> wrote: > > > > The beauty of a $2 arduino and a drop of code snitched from Engineer > google. > > OK enough of that back to the thread. > > Regards > > Paul > > WB8TSL > > > >> On Fri, Sep 14, 2018 at 8:04 PM, Mike Feher <mfeher@eozinc.com> wrote: > >> > >> Not when I built them in the late 60's and early 70's. All discrete. 73 > - > >> Mike > >> > >> > >> > >> Mike B. Feher, N4FS > >> > >> 89 Arnold Blvd. > >> > >> Howell NJ 07731 > >> > >> 848-245-9115 > >> > >> > >> > >> -----Original Message----- > >> From: time-nuts <time-nuts-bounces@lists.febo.com> On Behalf Of Richard > >> (Rick) Karlquist > >> Sent: Friday, September 14, 2018 7:15 PM > >> To: Discussion of precise time and frequency measurement > >> <time-nuts@lists.febo.com>; ed breya <eb@telight.com> > >> Subject: Re: [time-nuts] Programmable clock for BFO use....noise > >> > >> > >> > >> > >>> Finally, of course, you can use DDS. This is nearly an ideal case for > >> > >> > >> > >> The trouble with a DDS is that you need a microcontroller with software > >> just > >> to baby sit the thing. > >> > >> > >> > >> Rick N6RK > >> > >> > >> > >> _______________________________________________ > >> > >> time-nuts mailing list -- <mailto:time-nuts@lists.febo.com> > >> time-nuts@lists.febo.com To unsubscribe, go to > >> <http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com> > >> http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > >> > >> and follow the instructions there. > >> > >> _______________________________________________ > >> time-nuts mailing list -- time-nuts@lists.febo.com > >> To unsubscribe, go to http://lists.febo.com/mailman/ > >> listinfo/time-nuts_lists.febo.com > >> and follow the instructions there. > > _______________________________________________ > > time-nuts mailing list -- time-nuts@lists.febo.com > > To unsubscribe, go to http://lists.febo.com/mailman/ > listinfo/time-nuts_lists.febo.com > > and follow the instructions there. > > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to http://lists.febo.com/mailman/ > listinfo/time-nuts_lists.febo.com > and follow the instructions there. >

MD

Magnus Danielson

Sun, Sep 16, 2018 7:40 PM

Hi Chris,

On 09/16/2018 07:22 PM, Chris Waldrup wrote:

How about using a ProgRock on Hans Summers QRP Labs website? This is a programmable crystal replacement.

I have one of those but have not had the time to put it up for a real
test. Also got the GPS module that should fit, as you can train it to
slave a PPS. It would be interesting to take the setup for a test-ride.

Need to clean the desk with other things in order to be able to focus on
fun projects like that.

Cheers,
Magnus

Hi Chris, On 09/16/2018 07:22 PM, Chris Waldrup wrote: > How about using a ProgRock on Hans Summers QRP Labs website? This is a programmable crystal replacement. I have one of those but have not had the time to put it up for a real test. Also got the GPS module that should fit, as you can train it to slave a PPS. It would be interesting to take the setup for a test-ride. Need to clean the desk with other things in order to be able to focus on fun projects like that. Cheers, Magnus

GH

Gerhard Hoffmann

Sun, Sep 16, 2018 8:08 PM

Am 15.09.2018 um 17:38 schrieb Richard (Rick) Karlquist:

If you divide by something that is not a power of 2, then it is
important
that each stage produces an output waveform with a 50% duty cycle.
Otherwise
flicker noise which has been up-mixed by a previous stage, will be
down-mixed
into the signal band, increasing the close-in phase-noise.

Wow, another thing I never knew. The conventional wisdom was to
divide by any number (even or odd) and then follow that divider
with a divide by 2 flip flop to get 50%. Now, that is in question.
The now correct answer is to us a variable modulus prescaler to
divide by P and P+1, controlled by a toggle flip flop to make
half the divisions at P and half at P+1.

Resynchronize the output of the divider to the undivided clock with
another D-FF
and everything but that last D-FF will fall out of the equation for
phase noise.

I'm also not a fan of using slowish, slew-rate challenged logic as a
replacement
for a low pass. When I want a low pass, I make it from nice,
time-invariant RLC.

regards, Gerhard.

Am 15.09.2018 um 17:38 schrieb Richard (Rick) Karlquist: > >> If you divide by something that is not a power of 2, then it is >> important >> that each stage produces an output waveform with a 50% duty cycle. >> Otherwise >> flicker noise which has been up-mixed by a previous stage, will be >> down-mixed >> into the signal band, increasing the close-in phase-noise. > > Wow, another thing I never knew. The conventional wisdom was to > divide by any number (even or odd) and then follow that divider > with a divide by 2 flip flop to get 50%. Now, that is in question. > The now correct answer is to us a variable modulus prescaler to > divide by P and P+1, controlled by a toggle flip flop to make > half the divisions at P and half at P+1. Resynchronize the output of the divider to the undivided clock with another D-FF and everything but that last D-FF will fall out of the equation for phase noise. I'm also not a fan of using slowish, slew-rate challenged logic as a replacement for a low pass. When I want a low pass, I make it from nice, time-invariant RLC. regards, Gerhard.