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RSSI implementation

GA
Ghassan Ameer
Mon, Aug 10, 2015 4:26 PM

Hi,
Sorry if you got this email before, but I tried to email support@ettus.commailto:support@ettus.com, but I got no reply so I thought this email I should send my questions to.

I just bought a USRP B200 board. I'm planning on using it for GNSS/Telecomms applications. I would like to implement an RSSI module on the FPGA, although by looking at the AD9361 RF chip datasheet, I can see that there is an internal RSSI module. Also I looked into the UHD software a found a function called get_rssi which I can call by using get_rx_sensor('rssi',0). This returns to me a steady value between -55 to -61 [dBm I believe]. This value doesn't change even by applying a signal to the RF input or changing the gain ,which led me to think that the AGC is enabled.

I'm using the master repository code since it has the addition of user settings functionality

My questions summarised are :

  1. Is there an RSSI module on the b200 board?

  2. Is the RF chip's AGC enabled, if yes how can I disable it and enable manual gain control ?

  3. If there is an RSSI module, why does the RSSI value not change when the input power changes? [assuming agc is disabled]?

  4. How do I make a register from the FPGA available for reading within the host code, I found a section called user_settings  in the FPGA and the host code which I presume for this functionality?

I hope you can enlighten me with your answers.

Kind regards,
Ghassan

Ghassan Ameer
Networks and Systems

[Email Sig]

Satellite Applications Catapult Ltd
Electron Building, Fermi Avenue,
Harwell Oxford, Didcot, Oxfordshire,
OX11 0QR, UK

Reception :  +44 (0) 1235 567999
Email:  ghassan.ameer@sa.catapult.org.ukmailto:ghassan.ameer@sa.catapult.org.uk
Website:  sa.catapult.org.ukhttp://www.sa.catapult.org.uk/

CATAPULT OPEN

This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult.

Hi, Sorry if you got this email before, but I tried to email support@ettus.com<mailto:support@ettus.com>, but I got no reply so I thought this email I should send my questions to. I just bought a USRP B200 board. I'm planning on using it for GNSS/Telecomms applications. I would like to implement an RSSI module on the FPGA, although by looking at the AD9361 RF chip datasheet, I can see that there is an internal RSSI module. Also I looked into the UHD software a found a function called get_rssi which I can call by using get_rx_sensor('rssi',0). This returns to me a steady value between -55 to -61 [dBm I believe]. This value doesn't change even by applying a signal to the RF input or changing the gain ,which led me to think that the AGC is enabled. I'm using the master repository code since it has the addition of user settings functionality My questions summarised are : 1) Is there an RSSI module on the b200 board? 2) Is the RF chip's AGC enabled, if yes how can I disable it and enable manual gain control ? 3) If there is an RSSI module, why does the RSSI value not change when the input power changes? [assuming agc is disabled]? 4) How do I make a register from the FPGA available for reading within the host code, I found a section called user_settings in the FPGA and the host code which I presume for this functionality? I hope you can enlighten me with your answers. Kind regards, Ghassan Ghassan Ameer Networks and Systems [Email Sig] Satellite Applications Catapult Ltd Electron Building, Fermi Avenue, Harwell Oxford, Didcot, Oxfordshire, OX11 0QR, UK Reception : +44 (0) 1235 567999 Email: ghassan.ameer@sa.catapult.org.uk<mailto:ghassan.ameer@sa.catapult.org.uk> Website: sa.catapult.org.uk<http://www.sa.catapult.org.uk/> CATAPULT OPEN This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult.
Attached image
MD
Marcus D. Leech
Mon, Aug 10, 2015 4:38 PM

On 08/10/2015 12:26 PM, Ghassan Ameer via USRP-users wrote:

Hi,

Sorry if you got this email before, but I tried to email
support@ettus.com mailto:support@ettus.com, but I got no reply so I
thought this email I should send my questions to.

I just bought a USRP B200 board. I'm planning on using it for
GNSS/Telecomms applications. I would like to implement an RSSI module
on the FPGA, although by looking at the AD9361 RF chip datasheet, I
can see that there is an internal RSSI module. Also I looked into the
UHD software a found a function called get_rssi which I can call by
using get_rx_sensor('rssi',0). This returns to me a steady value
between -55 to -61 [dBm I believe]. This value doesn't change even by
applying a signal to the RF input or changing the gain ,which led me
to think that the AGC is enabled.

I’m using the master repository code since it has the addition of user
settings functionality

My questions summarised are :

  1. Is there an RSSI module on the b200 board?

I don't think the RSSI subsystem on the AD9361 is actually used for
anything.

  1. Is the RF chip’s AGC enabled, if yes how can I disable it and
    enable manual gain control ?

AGC is not enabled on the B2xx, it's always manual.

  1. If there is an RSSI module, why does the RSSI value not change when
    the input power changes? [assuming agc is disabled]?

  2. How do I make a register from the FPGA available for reading
    within the host code, I found a section called user_settings  in the
    FPGA and the host code which I presume for this functionality?

The problem with hardware RSSI is that it nearly-never "maps" into the
bandwidth of the signals you're ultimately processing, so it can vary from
somewhat misleading to wildly misleading.

Calculating an RSSI value on the sample stream that you ultimately
receive on the host is pretty easy:

RSSI ~=  AVG(II+QQ)  and then scale to taste.

If you're already processing samples in real-time on the host anyway,
adding this calculation doesn't significantly increase your compute
footprint.

You can do that on the FPGA as well, but I'm not the best person to
advise on how to do that.

I hope you can enlighten me with your answers.

Kind regards,

Ghassan

Ghassan Ameer

Networks and Systems

Email Sig

Satellite Applications Catapult Ltd

Electron Building, Fermi Avenue,

Harwell Oxford, Didcot, Oxfordshire,

OX11 0QR, UK

Reception :  +44 (0) 1235 567999

Email: ghassan.ameer@sa.catapult.org.uk
mailto:ghassan.ameer@sa.catapult.org.uk

Website: sa.catapult.org.uk http://www.sa.catapult.org.uk/

CATAPULT OPEN

This e-mail and any attachments are confidential and intended solely
for the use of the recipient(s) to whom they are addressed. If you
have received it in error, please destroy all copies and inform the
sender. This email and any attachments are believed to be free from
viruses but the Satellite Applications Catapult accepts no liability
in connection therewith. Any views or opinions presented in this email
are solely those of the author and do not necessarily represent those
of Satellite Applications Catapult.

USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

On 08/10/2015 12:26 PM, Ghassan Ameer via USRP-users wrote: > > Hi, > > Sorry if you got this email before, but I tried to email > support@ettus.com <mailto:support@ettus.com>, but I got no reply so I > thought this email I should send my questions to. > > I just bought a USRP B200 board. I'm planning on using it for > GNSS/Telecomms applications. I would like to implement an RSSI module > on the FPGA, although by looking at the AD9361 RF chip datasheet, I > can see that there is an internal RSSI module. Also I looked into the > UHD software a found a function called get_rssi which I can call by > using get_rx_sensor('rssi',0). This returns to me a steady value > between -55 to -61 [dBm I believe]. This value doesn't change even by > applying a signal to the RF input or changing the gain ,which led me > to think that the AGC is enabled. > > I’m using the master repository code since it has the addition of user > settings functionality > > My questions summarised are : > > 1) Is there an RSSI module on the b200 board? > I don't think the RSSI subsystem on the AD9361 is actually used for anything. > 2) Is the RF chip’s AGC enabled, if yes how can I disable it and > enable manual gain control ? > AGC is not enabled on the B2xx, it's always manual. > 3) If there is an RSSI module, why does the RSSI value not change when > the input power changes? [assuming agc is disabled]? > > 4) How do I make a register from the FPGA available for reading > within the host code, I found a section called user_settings in the > FPGA and the host code which I presume for this functionality? > The problem with hardware RSSI is that it nearly-never "maps" into the bandwidth of the signals you're ultimately processing, so it can vary from somewhat misleading to wildly misleading. Calculating an RSSI value on the sample stream that you ultimately receive on the host is pretty easy: RSSI ~= AVG(I*I+Q*Q) and then scale to taste. If you're already processing samples in real-time on the host anyway, adding this calculation doesn't significantly increase your compute footprint. You *can* do that on the FPGA as well, but I'm not the best person to advise on how to do that. > I hope you can enlighten me with your answers. > > Kind regards, > > Ghassan > > *Ghassan Ameer* > > Networks and Systems > > Email Sig > > *Satellite Applications Catapult Ltd* > > Electron Building, Fermi Avenue, > > Harwell Oxford, Didcot, Oxfordshire, > > OX11 0QR, UK > > Reception : +44 (0) 1235 567999 > > Email: _ghassan.ameer@sa.catapult.org.uk > <mailto:ghassan.ameer@sa.catapult.org.uk>_ > > Website: sa.catapult.org.uk <http://www.sa.catapult.org.uk/> > > *CATAPULT OPEN* > > This e-mail and any attachments are confidential and intended solely > for the use of the recipient(s) to whom they are addressed. If you > have received it in error, please destroy all copies and inform the > sender. This email and any attachments are believed to be free from > viruses but the Satellite Applications Catapult accepts no liability > in connection therewith. Any views or opinions presented in this email > are solely those of the author and do not necessarily represent those > of Satellite Applications Catapult. > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Attached image
GA
Ghassan Ameer
Mon, Aug 10, 2015 4:53 PM

Hi Marcus,
Thanks for your quick reply. I already have implemented an RSSI module on the FPGA. My question is How do I read the register value on the host. I know that setting_reg module on the FPGA is write only. But in the master repository code, a new user_settings section was added in radio_b200.v, which includes an example of setting and reading back of custom user registers. I'm trying to understand what do I need to change in this template in order to add my own register.

Regards,
Ghassan

From: USRP-users [mailto:usrp-users-bounces@lists.ettus.com] On Behalf Of Marcus D. Leech via USRP-users
Sent: 10 August 2015 17:38
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] RSSI implementation

On 08/10/2015 12:26 PM, Ghassan Ameer via USRP-users wrote:
Hi,
Sorry if you got this email before, but I tried to email support@ettus.commailto:support@ettus.com, but I got no reply so I thought this email I should send my questions to.

I just bought a USRP B200 board. I'm planning on using it for GNSS/Telecomms applications. I would like to implement an RSSI module on the FPGA, although by looking at the AD9361 RF chip datasheet, I can see that there is an internal RSSI module. Also I looked into the UHD software a found a function called get_rssi which I can call by using get_rx_sensor('rssi',0). This returns to me a steady value between -55 to -61 [dBm I believe]. This value doesn't change even by applying a signal to the RF input or changing the gain ,which led me to think that the AGC is enabled.

I'm using the master repository code since it has the addition of user settings functionality

My questions summarised are :

  1. Is there an RSSI module on the b200 board?
    I don't think the RSSI subsystem on the AD9361 is actually used for anything.

  2. Is the RF chip's AGC enabled, if yes how can I disable it and enable manual gain control ?
    AGC is not enabled on the B2xx, it's always manual.

  3. If there is an RSSI module, why does the RSSI value not change when the input power changes? [assuming agc is disabled]?

  4. How do I make a register from the FPGA available for reading within the host code, I found a section called user_settings  in the FPGA and the host code which I presume for this functionality?
    The problem with hardware RSSI is that it nearly-never "maps" into the bandwidth of the signals you're ultimately processing, so it can vary from
    somewhat misleading to wildly misleading.

Calculating an RSSI value on the sample stream that you ultimately receive on the host is pretty easy:

RSSI ~=  AVG(II+QQ)  and then scale to taste.

If you're already processing samples in real-time on the host anyway, adding this calculation doesn't significantly increase your compute footprint.

You can do that on the FPGA as well, but I'm not the best person to advise on how to do that.

I hope you can enlighten me with your answers.

Kind regards,
Ghassan

Ghassan Ameer
Networks and Systems

[Email                Sig]

Satellite Applications Catapult Ltd
Electron Building, Fermi Avenue,
Harwell Oxford, Didcot, Oxfordshire,
OX11 0QR, UK

Reception :  +44 (0) 1235 567999
Email:  ghassan.ameer@sa.catapult.org.ukmailto:ghassan.ameer@sa.catapult.org.uk
Website:  sa.catapult.org.ukhttp://www.sa.catapult.org.uk/

CATAPULT OPEN

This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult.

USRP-users mailing list

USRP-users@lists.ettus.commailto:USRP-users@lists.ettus.com

http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult.

Hi Marcus, Thanks for your quick reply. I already have implemented an RSSI module on the FPGA. My question is How do I read the register value on the host. I know that setting_reg module on the FPGA is write only. But in the master repository code, a new user_settings section was added in radio_b200.v, which includes an example of setting and reading back of custom user registers. I'm trying to understand what do I need to change in this template in order to add my own register. Regards, Ghassan From: USRP-users [mailto:usrp-users-bounces@lists.ettus.com] On Behalf Of Marcus D. Leech via USRP-users Sent: 10 August 2015 17:38 To: usrp-users@lists.ettus.com Subject: Re: [USRP-users] RSSI implementation On 08/10/2015 12:26 PM, Ghassan Ameer via USRP-users wrote: Hi, Sorry if you got this email before, but I tried to email support@ettus.com<mailto:support@ettus.com>, but I got no reply so I thought this email I should send my questions to. I just bought a USRP B200 board. I'm planning on using it for GNSS/Telecomms applications. I would like to implement an RSSI module on the FPGA, although by looking at the AD9361 RF chip datasheet, I can see that there is an internal RSSI module. Also I looked into the UHD software a found a function called get_rssi which I can call by using get_rx_sensor('rssi',0). This returns to me a steady value between -55 to -61 [dBm I believe]. This value doesn't change even by applying a signal to the RF input or changing the gain ,which led me to think that the AGC is enabled. I'm using the master repository code since it has the addition of user settings functionality My questions summarised are : 1) Is there an RSSI module on the b200 board? I don't think the RSSI subsystem on the AD9361 is actually used for anything. 2) Is the RF chip's AGC enabled, if yes how can I disable it and enable manual gain control ? AGC is not enabled on the B2xx, it's always manual. 3) If there is an RSSI module, why does the RSSI value not change when the input power changes? [assuming agc is disabled]? 4) How do I make a register from the FPGA available for reading within the host code, I found a section called user_settings in the FPGA and the host code which I presume for this functionality? The problem with hardware RSSI is that it nearly-never "maps" into the bandwidth of the signals you're ultimately processing, so it can vary from somewhat misleading to wildly misleading. Calculating an RSSI value on the sample stream that you ultimately receive on the host is pretty easy: RSSI ~= AVG(I*I+Q*Q) and then scale to taste. If you're already processing samples in real-time on the host anyway, adding this calculation doesn't significantly increase your compute footprint. You *can* do that on the FPGA as well, but I'm not the best person to advise on how to do that. I hope you can enlighten me with your answers. Kind regards, Ghassan Ghassan Ameer Networks and Systems [Email Sig] Satellite Applications Catapult Ltd Electron Building, Fermi Avenue, Harwell Oxford, Didcot, Oxfordshire, OX11 0QR, UK Reception : +44 (0) 1235 567999 Email: ghassan.ameer@sa.catapult.org.uk<mailto:ghassan.ameer@sa.catapult.org.uk> Website: sa.catapult.org.uk<http://www.sa.catapult.org.uk/> CATAPULT OPEN This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult. _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult.
Attached image
IB
Ian Buckley
Mon, Aug 10, 2015 4:55 PM

Ghassan,
The user_settings functionality adds a private bus for custom FPGA development that can have upto 256 32bit registers. It's a standard piece of code that we include in most USRP's but in the case of B200 it's currently disabled in the FPGA build be default because UHD currently doesn't have the B200 specific code to supply this user API.

The API call to the AD9361 RSSI was added about 6 months ago and tested to be working at that time. I've not encountered anybody who is actively using it at this time. Your best resource is to read ADI's technical literature on the AD9361 as it's a remarkably complex radio IC.

-Ian

  1. How do I make a register from the FPGA available for reading within the host code, I found a section called user_settings  in the FPGA and the host code which I presume for this functionality?

I hope you can enlighten me with your answers.

Kind regards,
Ghassan

Ghassan Ameer
Networks and Systems

<image001.png>

Satellite Applications Catapult Ltd
Electron Building, Fermi Avenue,
Harwell Oxford, Didcot, Oxfordshire,
OX11 0QR, UK

Reception :  +44 (0) 1235 567999
Email:  ghassan.ameer@sa.catapult.org.uk
Website:  sa.catapult.org.uk

CATAPULT OPEN

This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult. _______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Ghassan, The user_settings functionality adds a private bus for custom FPGA development that can have upto 256 32bit registers. It's a standard piece of code that we include in most USRP's but in the case of B200 it's currently disabled in the FPGA build be default because UHD currently doesn't have the B200 specific code to supply this user API. The API call to the AD9361 RSSI was added about 6 months ago and tested to be working at that time. I've not encountered anybody who is actively using it at this time. Your best resource is to read ADI's technical literature on the AD9361 as it's a remarkably complex radio IC. -Ian > > 4) How do I make a register from the FPGA available for reading within the host code, I found a section called user_settings in the FPGA and the host code which I presume for this functionality? > > I hope you can enlighten me with your answers. > > Kind regards, > Ghassan > > > > Ghassan Ameer > Networks and Systems > > <image001.png> > > > Satellite Applications Catapult Ltd > Electron Building, Fermi Avenue, > Harwell Oxford, Didcot, Oxfordshire, > OX11 0QR, UK > > Reception : +44 (0) 1235 567999 > Email: ghassan.ameer@sa.catapult.org.uk > Website: sa.catapult.org.uk > > CATAPULT OPEN > > This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult. _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
IB
Ian Buckley
Mon, Aug 10, 2015 5:00 PM

Ghassan,
in the short term you could just follow the template of existing setting_regs (read is effected via the read back bus..search for rb_addr and rb_data) in UHD. The problem being that normal setting regs are not exposed directly via a user API so you are constrained to work within a scope internal to UHD which makes future code merges very problematic.

-Ian

On Aug 10, 2015, at 9:53 AM, Ghassan Ameer via USRP-users usrp-users@lists.ettus.com wrote:

Hi Marcus,
Thanks for your quick reply. I already have implemented an RSSI module on the FPGA. My question is How do I read the register value on the host. I know that setting_reg module on the FPGA is write only. But in the master repository code, a new user_settings section was added in radio_b200.v, which includes an example of setting and reading back of custom user registers. I’m trying to understand what do I need to change in this template in order to add my own register.

Regards,
Ghassan

From: USRP-users [mailto:usrp-users-bounces@lists.ettus.com] On Behalf Of Marcus D. Leech via USRP-users
Sent: 10 August 2015 17:38
To: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] RSSI implementation

On 08/10/2015 12:26 PM, Ghassan Ameer via USRP-users wrote:
Hi,
Sorry if you got this email before, but I tried to email support@ettus.com, but I got no reply so I thought this email I should send my questions to.

I just bought a USRP B200 board. I'm planning on using it for GNSS/Telecomms applications. I would like to implement an RSSI module on the FPGA, although by looking at the AD9361 RF chip datasheet, I can see that there is an internal RSSI module. Also I looked into the UHD software a found a function called get_rssi which I can call by using get_rx_sensor('rssi',0). This returns to me a steady value between -55 to -61 [dBm I believe]. This value doesn't change even by applying a signal to the RF input or changing the gain ,which led me to think that the AGC is enabled.

I’m using the master repository code since it has the addition of user settings functionality

My questions summarised are :

  1. Is there an RSSI module on the b200 board?
    I don't think the RSSI subsystem on the AD9361 is actually used for anything.

  2. Is the RF chip’s AGC enabled, if yes how can I disable it and enable manual gain control ?
    AGC is not enabled on the B2xx, it's always manual.

  3. If there is an RSSI module, why does the RSSI value not change when the input power changes? [assuming agc is disabled]?

  4. How do I make a register from the FPGA available for reading within the host code, I found a section called user_settings  in the FPGA and the host code which I presume for this functionality?
    The problem with hardware RSSI is that it nearly-never "maps" into the bandwidth of the signals you're ultimately processing, so it can vary from
    somewhat misleading to wildly misleading.

Calculating an RSSI value on the sample stream that you ultimately receive on the host is pretty easy:

RSSI ~=  AVG(II+QQ)  and then scale to taste.

If you're already processing samples in real-time on the host anyway, adding this calculation doesn't significantly increase your compute footprint.

You can do that on the FPGA as well, but I'm not the best person to advise on how to do that.

I hope you can enlighten me with your answers.

Kind regards,
Ghassan

Ghassan Ameer
Networks and Systems

<image001.png>

Satellite Applications Catapult Ltd
Electron Building, Fermi Avenue,
Harwell Oxford, Didcot, Oxfordshire,
OX11 0QR, UK

Reception :  +44 (0) 1235 567999
Email:  ghassan.ameer@sa.catapult.org.uk
Website:  sa.catapult.org.uk

CATAPULT OPEN

This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult.

USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult. _______________________________________________
USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Ghassan, in the short term you could just follow the template of existing setting_regs (read is effected via the read back bus..search for rb_addr and rb_data) in UHD. The problem being that normal setting regs are not exposed directly via a user API so you are constrained to work within a scope internal to UHD which makes future code merges very problematic. -Ian On Aug 10, 2015, at 9:53 AM, Ghassan Ameer via USRP-users <usrp-users@lists.ettus.com> wrote: > Hi Marcus, > Thanks for your quick reply. I already have implemented an RSSI module on the FPGA. My question is How do I read the register value on the host. I know that setting_reg module on the FPGA is write only. But in the master repository code, a new user_settings section was added in radio_b200.v, which includes an example of setting and reading back of custom user registers. I’m trying to understand what do I need to change in this template in order to add my own register. > > Regards, > Ghassan > > > > From: USRP-users [mailto:usrp-users-bounces@lists.ettus.com] On Behalf Of Marcus D. Leech via USRP-users > Sent: 10 August 2015 17:38 > To: usrp-users@lists.ettus.com > Subject: Re: [USRP-users] RSSI implementation > > On 08/10/2015 12:26 PM, Ghassan Ameer via USRP-users wrote: > Hi, > Sorry if you got this email before, but I tried to email support@ettus.com, but I got no reply so I thought this email I should send my questions to. > > I just bought a USRP B200 board. I'm planning on using it for GNSS/Telecomms applications. I would like to implement an RSSI module on the FPGA, although by looking at the AD9361 RF chip datasheet, I can see that there is an internal RSSI module. Also I looked into the UHD software a found a function called get_rssi which I can call by using get_rx_sensor('rssi',0). This returns to me a steady value between -55 to -61 [dBm I believe]. This value doesn't change even by applying a signal to the RF input or changing the gain ,which led me to think that the AGC is enabled. > > I’m using the master repository code since it has the addition of user settings functionality > > My questions summarised are : > > 1) Is there an RSSI module on the b200 board? > I don't think the RSSI subsystem on the AD9361 is actually used for anything. > > > > 2) Is the RF chip’s AGC enabled, if yes how can I disable it and enable manual gain control ? > AGC is not enabled on the B2xx, it's always manual. > > > > 3) If there is an RSSI module, why does the RSSI value not change when the input power changes? [assuming agc is disabled]? > > 4) How do I make a register from the FPGA available for reading within the host code, I found a section called user_settings in the FPGA and the host code which I presume for this functionality? > The problem with hardware RSSI is that it nearly-never "maps" into the bandwidth of the signals you're ultimately processing, so it can vary from > somewhat misleading to wildly misleading. > > Calculating an RSSI value on the sample stream that you ultimately receive on the host is pretty easy: > > RSSI ~= AVG(I*I+Q*Q) and then scale to taste. > > If you're already processing samples in real-time on the host anyway, adding this calculation doesn't significantly increase your compute footprint. > > You *can* do that on the FPGA as well, but I'm not the best person to advise on how to do that. > > > > I hope you can enlighten me with your answers. > > Kind regards, > Ghassan > > > > Ghassan Ameer > Networks and Systems > > <image001.png> > > > Satellite Applications Catapult Ltd > Electron Building, Fermi Avenue, > Harwell Oxford, Didcot, Oxfordshire, > OX11 0QR, UK > > Reception : +44 (0) 1235 567999 > Email: ghassan.ameer@sa.catapult.org.uk > Website: sa.catapult.org.uk > > CATAPULT OPEN > > This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult. > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult. _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
MB
Martin Braun
Mon, Aug 10, 2015 5:59 PM

On 10.08.2015 09:38, Marcus D. Leech via USRP-users wrote:

  1. Is there an RSSI module on the b200 board?

I don't think the RSSI subsystem on the AD9361 is actually used for anything.

You can, however, use the 'rssi' sensor through the sensor API. Do check
the Ad936x datasheets if this meets your specs, it's not something that
we've implemented, we merely expose that feature of the chip.

  1. Is the RF chip’s AGC enabled, if yes how can I disable it and
    enable manual gain control ?

AGC is not enabled on the B2xx, it's always manual.

We're actually currently playing around with AGC on master branch.
There's a function on multi_usrp called set_rx_agc() which you can use
to turn it on and off. AD936x supports different AGC modes, too, which
are in theory available through UHD, but we don't have a simple API for
them.

M

On 10.08.2015 09:38, Marcus D. Leech via USRP-users wrote: >> 1) Is there an RSSI module on the b200 board? > I don't think the RSSI subsystem on the AD9361 is actually used for anything. You can, however, use the 'rssi' sensor through the sensor API. Do check the Ad936x datasheets if this meets your specs, it's not something that we've implemented, we merely expose that feature of the chip. >> 2) Is the RF chip’s AGC enabled, if yes how can I disable it and >> enable manual gain control ? >> > AGC is not enabled on the B2xx, it's always manual. We're actually currently playing around with AGC on master branch. There's a function on multi_usrp called set_rx_agc() which you can use to turn it on and off. AD936x supports different AGC modes, too, which are in theory available through UHD, but we don't have a simple API for them. M
MD
Marcus D. Leech
Mon, Aug 10, 2015 6:06 PM

On 08/10/2015 01:59 PM, Martin Braun via USRP-users wrote:

On 10.08.2015 09:38, Marcus D. Leech via USRP-users wrote:

  1. Is there an RSSI module on the b200 board?

I don't think the RSSI subsystem on the AD9361 is actually used for anything.

You can, however, use the 'rssi' sensor through the sensor API. Do check
the Ad936x datasheets if this meets your specs, it's not something that
we've implemented, we merely expose that feature of the chip.

Ah, I had thought that it wasn't implemented at all, but clearly my
mental cache needs to be updated.

Although I will once again opine that a hardware analog RSSI can be
anywhere from nearly-correct to wildly misleading, because its
"field of view" may be very different than your actual signal
bandwidth.  That may, of course, be what you want, or it may not.

  1. Is the RF chip’s AGC enabled, if yes how can I disable it and
    enable manual gain control ?

AGC is not enabled on the B2xx, it's always manual.

We're actually currently playing around with AGC on master branch.
There's a function on multi_usrp called set_rx_agc() which you can use
to turn it on and off. AD936x supports different AGC modes, too, which
are in theory available through UHD, but we don't have a simple API for

It has historically been the case that the Ettus daughtercards don't
implement AGC, with occasional exceptions like the TVRX2, which has an
always-on AGC.  So, AGC isn't something that has had a lot of
attention paid to it up until now--usually any kind of
auto-level-setting is done
in the DSP flow inside the user application, with a fixed hardware
gain.  That's usually, but not always, "more than good enough".

them.

M

USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

On 08/10/2015 01:59 PM, Martin Braun via USRP-users wrote: > On 10.08.2015 09:38, Marcus D. Leech via USRP-users wrote: >>> 1) Is there an RSSI module on the b200 board? >> I don't think the RSSI subsystem on the AD9361 is actually used for anything. > You can, however, use the 'rssi' sensor through the sensor API. Do check > the Ad936x datasheets if this meets your specs, it's not something that > we've implemented, we merely expose that feature of the chip. Ah, I had thought that it wasn't implemented at all, but clearly my mental cache needs to be updated. Although I will once again opine that a hardware analog RSSI can be anywhere from nearly-correct to wildly misleading, because its "field of view" may be very different than your actual signal bandwidth. That may, of course, be what you want, or it may not. > >>> 2) Is the RF chip’s AGC enabled, if yes how can I disable it and >>> enable manual gain control ? >>> >> AGC is not enabled on the B2xx, it's always manual. > We're actually currently playing around with AGC on master branch. > There's a function on multi_usrp called set_rx_agc() which you can use > to turn it on and off. AD936x supports different AGC modes, too, which > are in theory available through UHD, but we don't have a simple API for It has historically been the case that the Ettus daughtercards don't implement AGC, with occasional exceptions like the TVRX2, which has an always-on AGC. So, AGC isn't something that has had a lot of attention paid to it up until now--usually any kind of auto-level-setting is done in the DSP flow inside the user application, with a fixed hardware gain. That's usually, but not always, "more than good enough". > them. > > M > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
MM
Marcus Müller
Mon, Aug 10, 2015 6:50 PM

Hi Ghassan,

I'm sorry we didn't react earlier; we did receive your mail on Thursday,
but a lot of people were travelling, and hence there was a delay.
So, to answer your questions:

  1. Is there an RSSI module on the b200 board?

Yes. The AD9361, the big chip that includes the ADC, mixers, filters and
amplifiers, is in fact able to do RSSI measurements.
However, be a little warned: RSSI is defined just as a vendor wants it
to behave, so how well your signal matches that depends on how well the
RSSI measurement matches the characteristics of your signal. You can
prescale and weight the measurement, so literature of the AD9361 Manual
is probably inevitable.

  1. Is the RF chip’s AGC enabled, if yes how can I disable it and
    enable manual gain control ?

No, AGC is not used, at that is only useful for specific applications.
There's something coming up about adjustable AGC, though, I think.

  1. If there is an RSSI module, why does the RSSI value not change
    when the input power changes? [assuming agc is disabled]?

That's a good question; I'm currently trying to reproduce the
phenomenon, but have another problem right now I need to solve first.

  1. How do I make a register from the FPGA available for reading
    within the host code, I found a section called user_settings  in the
    FPGA and the host code which I presume for this functionality?

I think Ian has covered that much better than I could.

Best regards,
Marcus

On 10.08.2015 18:26, Ghassan Ameer via USRP-users wrote:

Hi,

Sorry if you got this email before, but I tried to email
support@ettus.com mailto:support@ettus.com, but I got no reply so I
thought this email I should send my questions to.

I just bought a USRP B200 board. I'm planning on using it for
GNSS/Telecomms applications. I would like to implement an RSSI module
on the FPGA, although by looking at the AD9361 RF chip datasheet, I
can see that there is an internal RSSI module. Also I looked into the
UHD software a found a function called get_rssi which I can call by
using get_rx_sensor('rssi',0). This returns to me a steady value
between -55 to -61 [dBm I believe]. This value doesn't change even by
applying a signal to the RF input or changing the gain ,which led me
to think that the AGC is enabled.

I’m using the master repository code since it has the addition of user
settings functionality

My questions summarised are :

  1. Is there an RSSI module on the b200 board?

  2. Is the RF chip’s AGC enabled, if yes how can I disable it and
    enable manual gain control ?

  3. If there is an RSSI module, why does the RSSI value not change when
    the input power changes? [assuming agc is disabled]?

  4. How do I make a register from the FPGA available for reading
    within the host code, I found a section called user_settings  in the
    FPGA and the host code which I presume for this functionality?

I hope you can enlighten me with your answers.

Kind regards,

Ghassan

Ghassan Ameer

Networks and Systems

Email Sig

Satellite Applications Catapult Ltd

Electron Building, Fermi Avenue,

Harwell Oxford, Didcot, Oxfordshire,

OX11 0QR, UK

Reception :  +44 (0) 1235 567999

Email:  ghassan.ameer@sa.catapult.org.uk
mailto:ghassan.ameer@sa.catapult.org.uk

Website:  sa.catapult.org.uk http://www.sa.catapult.org.uk/

CATAPULT OPEN

This e-mail and any attachments are confidential and intended solely
for the use of the recipient(s) to whom they are addressed. If you
have received it in error, please destroy all copies and inform the
sender. This email and any attachments are believed to be free from
viruses but the Satellite Applications Catapult accepts no liability
in connection therewith. Any views or opinions presented in this email
are solely those of the author and do not necessarily represent those
of Satellite Applications Catapult.

USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Hi Ghassan, I'm sorry we didn't react earlier; we did receive your mail on Thursday, but a lot of people were travelling, and hence there was a delay. So, to answer your questions: > 1) Is there an RSSI module on the b200 board? Yes. The AD9361, the big chip that includes the ADC, mixers, filters and amplifiers, is in fact able to do RSSI measurements. However, be a little warned: RSSI is defined just as a vendor wants it to behave, so how well your signal matches that depends on how well the RSSI measurement matches the characteristics of your signal. You can prescale and weight the measurement, so literature of the AD9361 Manual is probably inevitable. > 2) Is the RF chip’s AGC enabled, if yes how can I disable it and > enable manual gain control ? No, AGC is not used, at that is only useful for specific applications. There's something coming up about adjustable AGC, though, I think. > 3) If there is an RSSI module, why does the RSSI value not change > when the input power changes? [assuming agc is disabled]? That's a good question; I'm currently trying to reproduce the phenomenon, but have another problem right now I need to solve first. > > 4) How do I make a register from the FPGA available for reading > within the host code, I found a section called user_settings in the > FPGA and the host code which I presume for this functionality? I think Ian has covered that much better than I could. Best regards, Marcus On 10.08.2015 18:26, Ghassan Ameer via USRP-users wrote: > > Hi, > > Sorry if you got this email before, but I tried to email > support@ettus.com <mailto:support@ettus.com>, but I got no reply so I > thought this email I should send my questions to. > > > > I just bought a USRP B200 board. I'm planning on using it for > GNSS/Telecomms applications. I would like to implement an RSSI module > on the FPGA, although by looking at the AD9361 RF chip datasheet, I > can see that there is an internal RSSI module. Also I looked into the > UHD software a found a function called get_rssi which I can call by > using get_rx_sensor('rssi',0). This returns to me a steady value > between -55 to -61 [dBm I believe]. This value doesn't change even by > applying a signal to the RF input or changing the gain ,which led me > to think that the AGC is enabled. > > > > I’m using the master repository code since it has the addition of user > settings functionality > > > > My questions summarised are : > > > > 1) Is there an RSSI module on the b200 board? > > > > 2) Is the RF chip’s AGC enabled, if yes how can I disable it and > enable manual gain control ? > > > > 3) If there is an RSSI module, why does the RSSI value not change when > the input power changes? [assuming agc is disabled]? > > > > 4) How do I make a register from the FPGA available for reading > within the host code, I found a section called user_settings in the > FPGA and the host code which I presume for this functionality? > > > > I hope you can enlighten me with your answers. > > > > Kind regards, > > Ghassan > > > > > > > > *Ghassan Ameer* > > Networks and Systems > > > > Email Sig > > > > > > *Satellite Applications Catapult Ltd* > > Electron Building, Fermi Avenue, > > Harwell Oxford, Didcot, Oxfordshire, > > OX11 0QR, UK > > > > Reception : +44 (0) 1235 567999 > > Email: _ghassan.ameer@sa.catapult.org.uk > <mailto:ghassan.ameer@sa.catapult.org.uk>_ > > Website: sa.catapult.org.uk <http://www.sa.catapult.org.uk/> > > > > *CATAPULT OPEN* > > > > This e-mail and any attachments are confidential and intended solely > for the use of the recipient(s) to whom they are addressed. If you > have received it in error, please destroy all copies and inform the > sender. This email and any attachments are believed to be free from > viruses but the Satellite Applications Catapult accepts no liability > in connection therewith. Any views or opinions presented in this email > are solely those of the author and do not necessarily represent those > of Satellite Applications Catapult. > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
Attached image
JA
Julian Arnold
Tue, Aug 11, 2015 12:09 PM

Hi Ghassan,

I just double checked if the RSSI sensor we are exposing is really working.
Attached is a very basic program I just quickly put together to see if the
sensor is working.

The USRP was connected to a signal generator set to 2.4 GHz.
Here is what I got:

Signal generator output power, RSSI sensor value
-40dBm, -68.75
-50dBm, -78,5
-60dBm, -88.75

So the output is not calibrated at all (It also depends on the RX gain you
choose. In my example 50dB). However, the relative value seems to be pretty
OK which is what I would expect from the internal RSSI measurement.

I hope that helps and allows you to use the RSSI sensor.

Cheers,
Julian

On Mon, Aug 10, 2015 at 6:26 PM, Ghassan Ameer via USRP-users <
usrp-users@lists.ettus.com> wrote:

Hi,

Sorry if you got this email before, but I tried to email support@ettus.com,
but I got no reply so I thought this email I should send my questions to.

I just bought a USRP B200 board. I'm planning on using it for
GNSS/Telecomms applications. I would like to implement an RSSI module on
the FPGA, although by looking at the AD9361 RF chip datasheet, I can see
that there is an internal RSSI module. Also I looked into the UHD software
a found a function called get_rssi which I can call by using
get_rx_sensor('rssi',0). This returns to me a steady value between -55 to
-61 [dBm I believe]. This value doesn't change even by applying a signal to
the RF input or changing the gain ,which led me to think that the AGC is
enabled.

I’m using the master repository code since it has the addition of user
settings functionality

My questions summarised are :

  1. Is there an RSSI module on the b200 board?

  2. Is the RF chip’s AGC enabled, if yes how can I disable it and enable
    manual gain control ?

  3. If there is an RSSI module, why does the RSSI value not change when the
    input power changes? [assuming agc is disabled]?

  4. How do I make a register from the FPGA available for reading within
    the host code, I found a section called user_settings  in the FPGA and the
    host code which I presume for this functionality?

I hope you can enlighten me with your answers.

Kind regards,

Ghassan

Ghassan Ameer

Networks and Systems

[image: Email Sig]

Satellite Applications Catapult Ltd

Electron Building, Fermi Avenue,

Harwell Oxford, Didcot, Oxfordshire,

OX11 0QR, UK

Reception :  +44 (0) 1235 567999

Email:  ghassan.ameer@sa.catapult.org.uk
ghassan.ameer@sa.catapult.org.uk

Website:  sa.catapult.org.uk http://www.sa.catapult.org.uk/

CATAPULT OPEN

This e-mail and any attachments are confidential and intended solely for
the use of the recipient(s) to whom they are addressed. If you have
received it in error, please destroy all copies and inform the sender. This
email and any attachments are believed to be free from viruses but the
Satellite Applications Catapult accepts no liability in connection
therewith. Any views or opinions presented in this email are solely those
of the author and do not necessarily represent those of Satellite
Applications Catapult.

USRP-users mailing list
USRP-users@lists.ettus.com
http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

--
Julian Arnold

Hi Ghassan, I just double checked if the RSSI sensor we are exposing is really working. Attached is a very basic program I just quickly put together to see if the sensor is working. The USRP was connected to a signal generator set to 2.4 GHz. Here is what I got: Signal generator output power, RSSI sensor value -40dBm, -68.75 -50dBm, -78,5 -60dBm, -88.75 So the output is not calibrated at all (It also depends on the RX gain you choose. In my example 50dB). However, the relative value seems to be pretty OK which is what I would expect from the internal RSSI measurement. I hope that helps and allows you to use the RSSI sensor. Cheers, Julian On Mon, Aug 10, 2015 at 6:26 PM, Ghassan Ameer via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi, > > Sorry if you got this email before, but I tried to email support@ettus.com, > but I got no reply so I thought this email I should send my questions to. > > > > I just bought a USRP B200 board. I'm planning on using it for > GNSS/Telecomms applications. I would like to implement an RSSI module on > the FPGA, although by looking at the AD9361 RF chip datasheet, I can see > that there is an internal RSSI module. Also I looked into the UHD software > a found a function called get_rssi which I can call by using > get_rx_sensor('rssi',0). This returns to me a steady value between -55 to > -61 [dBm I believe]. This value doesn't change even by applying a signal to > the RF input or changing the gain ,which led me to think that the AGC is > enabled. > > > > I’m using the master repository code since it has the addition of user > settings functionality > > > > My questions summarised are : > > > > 1) Is there an RSSI module on the b200 board? > > > > 2) Is the RF chip’s AGC enabled, if yes how can I disable it and enable > manual gain control ? > > > > 3) If there is an RSSI module, why does the RSSI value not change when the > input power changes? [assuming agc is disabled]? > > > > 4) How do I make a register from the FPGA available for reading within > the host code, I found a section called user_settings in the FPGA and the > host code which I presume for this functionality? > > > > I hope you can enlighten me with your answers. > > > > Kind regards, > > Ghassan > > > > > > > > *Ghassan Ameer* > > Networks and Systems > > > > [image: Email Sig] > > > > > > *Satellite Applications Catapult Ltd* > > Electron Building, Fermi Avenue, > > Harwell Oxford, Didcot, Oxfordshire, > > OX11 0QR, UK > > > > Reception : +44 (0) 1235 567999 > > Email: *ghassan.ameer@sa.catapult.org.uk > <ghassan.ameer@sa.catapult.org.uk>* > > Website: sa.catapult.org.uk <http://www.sa.catapult.org.uk/> > > > > *CATAPULT OPEN* > > > This e-mail and any attachments are confidential and intended solely for > the use of the recipient(s) to whom they are addressed. If you have > received it in error, please destroy all copies and inform the sender. This > email and any attachments are believed to be free from viruses but the > Satellite Applications Catapult accepts no liability in connection > therewith. Any views or opinions presented in this email are solely those > of the author and do not necessarily represent those of Satellite > Applications Catapult. > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > -- Julian Arnold
Attached image
rssi_read_tool.tar.gz (2.23 KB)
GA
Ghassan Ameer
Fri, Aug 14, 2015 3:36 PM

Hi Ian,
I have managed to integrate my RSSI module into the FPGA and read the value from within the UHD after some modification. I want my rssi module to be connected directly to the RF chip FPGA baseband  interface. Currently I connect my rssi module to rx signal within radio_b200.v module with rx[31:20] for I_data and rx[15:4] for Q_data. Could confirm to me if this is correct ? also what is the frequency of radio_clk? I came across Catalina [I think] interface while reading the FPGA code and was wondering what  it is?

Regards,
Ghassan
From: Ian Buckley [mailto:ianb@ionconcepts.com]
Sent: 10 August 2015 18:01
To: Ghassan Ameer ghassan.ameer@sa.catapult.org.uk
Cc: usrp-users@lists.ettus.com
Subject: Re: [USRP-users] RSSI implementation

Ghassan,
in the short term you could just follow the template of existing setting_regs (read is effected via the read back bus..search for rb_addr and rb_data) in UHD. The problem being that normal setting regs are not exposed directly via a user API so you are constrained to work within a scope internal to UHD which makes future code merges very problematic.

-Ian

On Aug 10, 2015, at 9:53 AM, Ghassan Ameer via USRP-users <usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com> wrote:

Hi Marcus,
Thanks for your quick reply. I already have implemented an RSSI module on the FPGA. My question is How do I read the register value on the host. I know that setting_reg module on the FPGA is write only. But in the master repository code, a new user_settings section was added in radio_b200.v, which includes an example of setting and reading back of custom user registers. I'm trying to understand what do I need to change in this template in order to add my own register.

Regards,
Ghassan

From: USRP-users [mailto:usrp-users-bounces@lists.ettus.commailto:users-bounces@lists.ettus.com] On Behalf Of Marcus D. Leech via USRP-users
Sent: 10 August 2015 17:38
To: usrp-users@lists.ettus.commailto:usrp-users@lists.ettus.com
Subject: Re: [USRP-users] RSSI implementation

On 08/10/2015 12:26 PM, Ghassan Ameer via USRP-users wrote:
Hi,
Sorry if you got this email before, but I tried to email support@ettus.commailto:support@ettus.com, but I got no reply so I thought this email I should send my questions to.

I just bought a USRP B200 board. I'm planning on using it for GNSS/Telecomms applications. I would like to implement an RSSI module on the FPGA, although by looking at the AD9361 RF chip datasheet, I can see that there is an internal RSSI module. Also I looked into the UHD software a found a function called get_rssi which I can call by using get_rx_sensor('rssi',0). This returns to me a steady value between -55 to -61 [dBm I believe]. This value doesn't change even by applying a signal to the RF input or changing the gain ,which led me to think that the AGC is enabled.

I'm using the master repository code since it has the addition of user settings functionality

My questions summarised are :

  1. Is there an RSSI module on the b200 board?
    I don't think the RSSI subsystem on the AD9361 is actually used for anything.

  2. Is the RF chip's AGC enabled, if yes how can I disable it and enable manual gain control ?
    AGC is not enabled on the B2xx, it's always manual.

  3. If there is an RSSI module, why does the RSSI value not change when the input power changes? [assuming agc is disabled]?

  4. How do I make a register from the FPGA available for reading within the host code, I found a section called user_settings  in the FPGA and the host code which I presume for this functionality?
    The problem with hardware RSSI is that it nearly-never "maps" into the bandwidth of the signals you're ultimately processing, so it can vary from
    somewhat misleading to wildly misleading.

Calculating an RSSI value on the sample stream that you ultimately receive on the host is pretty easy:

RSSI ~=  AVG(II+QQ)  and then scale to taste.

If you're already processing samples in real-time on the host anyway, adding this calculation doesn't significantly increase your compute footprint.

You can do that on the FPGA as well, but I'm not the best person to advise on how to do that.

I hope you can enlighten me with your answers.

Kind regards,
Ghassan

Ghassan Ameer
Networks and Systems

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Satellite Applications Catapult Ltd
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Hi Ian, I have managed to integrate my RSSI module into the FPGA and read the value from within the UHD after some modification. I want my rssi module to be connected directly to the RF chip FPGA baseband interface. Currently I connect my rssi module to rx signal within radio_b200.v module with rx[31:20] for I_data and rx[15:4] for Q_data. Could confirm to me if this is correct ? also what is the frequency of radio_clk? I came across Catalina [I think] interface while reading the FPGA code and was wondering what it is? Regards, Ghassan From: Ian Buckley [mailto:ianb@ionconcepts.com] Sent: 10 August 2015 18:01 To: Ghassan Ameer <ghassan.ameer@sa.catapult.org.uk> Cc: usrp-users@lists.ettus.com Subject: Re: [USRP-users] RSSI implementation Ghassan, in the short term you could just follow the template of existing setting_regs (read is effected via the read back bus..search for rb_addr and rb_data) in UHD. The problem being that normal setting regs are not exposed directly via a user API so you are constrained to work within a scope internal to UHD which makes future code merges very problematic. -Ian On Aug 10, 2015, at 9:53 AM, Ghassan Ameer via USRP-users <usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com>> wrote: Hi Marcus, Thanks for your quick reply. I already have implemented an RSSI module on the FPGA. My question is How do I read the register value on the host. I know that setting_reg module on the FPGA is write only. But in the master repository code, a new user_settings section was added in radio_b200.v, which includes an example of setting and reading back of custom user registers. I'm trying to understand what do I need to change in this template in order to add my own register. Regards, Ghassan From: USRP-users [mailto:usrp-users-bounces@lists.ettus.com<mailto:users-bounces@lists.ettus.com>] On Behalf Of Marcus D. Leech via USRP-users Sent: 10 August 2015 17:38 To: usrp-users@lists.ettus.com<mailto:usrp-users@lists.ettus.com> Subject: Re: [USRP-users] RSSI implementation On 08/10/2015 12:26 PM, Ghassan Ameer via USRP-users wrote: Hi, Sorry if you got this email before, but I tried to email support@ettus.com<mailto:support@ettus.com>, but I got no reply so I thought this email I should send my questions to. I just bought a USRP B200 board. I'm planning on using it for GNSS/Telecomms applications. I would like to implement an RSSI module on the FPGA, although by looking at the AD9361 RF chip datasheet, I can see that there is an internal RSSI module. Also I looked into the UHD software a found a function called get_rssi which I can call by using get_rx_sensor('rssi',0). This returns to me a steady value between -55 to -61 [dBm I believe]. This value doesn't change even by applying a signal to the RF input or changing the gain ,which led me to think that the AGC is enabled. I'm using the master repository code since it has the addition of user settings functionality My questions summarised are : 1) Is there an RSSI module on the b200 board? I don't think the RSSI subsystem on the AD9361 is actually used for anything. 2) Is the RF chip's AGC enabled, if yes how can I disable it and enable manual gain control ? AGC is not enabled on the B2xx, it's always manual. 3) If there is an RSSI module, why does the RSSI value not change when the input power changes? [assuming agc is disabled]? 4) How do I make a register from the FPGA available for reading within the host code, I found a section called user_settings in the FPGA and the host code which I presume for this functionality? The problem with hardware RSSI is that it nearly-never "maps" into the bandwidth of the signals you're ultimately processing, so it can vary from somewhat misleading to wildly misleading. Calculating an RSSI value on the sample stream that you ultimately receive on the host is pretty easy: RSSI ~= AVG(I*I+Q*Q) and then scale to taste. If you're already processing samples in real-time on the host anyway, adding this calculation doesn't significantly increase your compute footprint. You *can* do that on the FPGA as well, but I'm not the best person to advise on how to do that. I hope you can enlighten me with your answers. Kind regards, Ghassan Ghassan Ameer Networks and Systems <image001.png> Satellite Applications Catapult Ltd Electron Building, Fermi Avenue, Harwell Oxford, Didcot, Oxfordshire, OX11 0QR, UK Reception : +44 (0) 1235 567999 Email: ghassan.ameer@sa.catapult.org.uk<mailto:ghassan.ameer@sa.catapult.org.uk> Website: sa.catapult.org.uk<http://www.sa.catapult.org.uk/> CATAPULT OPEN This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult. _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult. _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com This e-mail and any attachments are confidential and intended solely for the use of the recipient(s) to whom they are addressed. If you have received it in error, please destroy all copies and inform the sender. This email and any attachments are believed to be free from viruses but the Satellite Applications Catapult accepts no liability in connection therewith. Any views or opinions presented in this email are solely those of the author and do not necessarily represent those of Satellite Applications Catapult.
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