Empathy List Archives

I+Q

 Hi Ian,

 I have managed to integrate my RSSI module into the FPGA and read
 the value from within the UHD after some modification. I want my
 rssi module to be connected directly to the RF chip FPGA baseband
  interface. Currently I connect my rssi module to rx signal within
 radio_b200.v module with rx[31:20] for I_data and rx[15:4] for
 Q_data. Could confirm to me if this is correct ? also what is the
 frequency of radio_clk? I came across Catalina [I think] interface
 while reading the FPGA code and was wondering what  it is?

 Regards,

 Ghassan

 *From:*Ian Buckley [mailto:ianb@ionconcepts.com
 <http://ionconcepts.com>]
 *Sent:*10 August 2015 18:01
 *To:*Ghassan Ameer <ghassan.ameer@sa.catapult.org.uk
 <mailto:ghassan.ameer@sa.catapult.org.uk>>
 *Cc:*usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>
 *Subject:*Re: [USRP-users] RSSI implementation

 Ghassan,

 in the short term you could just follow the template of existing
 setting_regs (read is effected via the read back bus..search for
 rb_addr and rb_data) in UHD. The problem being that normal setting
 regs are not exposed directly via a user API so you are
 constrained to work within a scope internal to UHD which makes
 future code merges very problematic.

 -Ian

 On Aug 10, 2015, at 9:53 AM, Ghassan Ameer via USRP-users
 <usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>>
 wrote:

     Hi Marcus,

     Thanks for your quick reply. I already have implemented an
     RSSI module on the FPGA. My question is How do I read the
     register value on the host. I know that setting_reg module on
     the FPGA is write only. But in the master repository code, a
     new user_settings section was added in radio_b200.v, which
     includes an example of setting and reading back of custom user
     registers. I’m trying to understand what do I need to change
     in this template in order to add my own register.

     Regards,

     Ghassan

     *From:*USRP-users [mailto:usrp-users-bounces@lists.ettus.com
     <mailto:users-bounces@lists.ettus.com>]*On Behalf Of*Marcus D.
     Leech via USRP-users
     *Sent:*10 August 2015 17:38
     *To:*usrp-users@lists.ettus.com
     <mailto:usrp-users@lists.ettus.com>
     *Subject:*Re: [USRP-users] RSSI implementation

     On 08/10/2015 12:26 PM, Ghassan Ameer via USRP-users wrote:

         Hi,

         Sorry if you got this email before, but I tried to
         emailsupport@ettus.com <mailto:support@ettus.com>,but I
         got no reply so I thought this email I should send my
         questions to.

         I just bought a USRP B200 board. I'm planning on using it
         for GNSS/Telecomms applications. I would like to implement
         an RSSI module on the FPGA, although by looking at the
         AD9361 RF chip datasheet, I can see that there is an
         internal RSSI module. Also I looked into the UHD software
         a found a function called get_rssi which I can call by
         using get_rx_sensor('rssi',0). This returns to me a steady
         value between -55 to -61 [dBm I believe]. This value
         doesn't change even by applying a signal to the RF input
         or changing the gain ,which led me to think that the AGC
         is enabled.

         I’m using the master repository code since it has the
         addition of user settings functionality

         My questions summarised are :

         1) Is there an RSSI module on the b200 board?

     I don't think the RSSI subsystem on the AD9361 is actually
     used for anything.

         2) Is the RF chip’s AGC enabled, if yes how can I disable
         it and enable manual gain control ?

     AGC is not enabled on the B2xx, it's always manual.

         3) If there is an RSSI module, why does the RSSI value not
         change when the input power changes? [assuming agc is
         disabled]?

         4)  How do I make a register from the FPGA available for
         reading within the host code, I found a section called
         user_settings  in the FPGA and the host code which I
         presume for this functionality?

     The problem with hardware RSSI is that it nearly-never "maps"
     into the bandwidth of the signals you're ultimately
     processing, so it can vary from
       somewhat misleading to wildly misleading.

     Calculating an RSSI value on the sample stream that you
     ultimately receive on the host is pretty easy:

     RSSI ~=  AVG(I*I+Q*Q)   and then scale to taste.

     If you're already processing samples in real-time on the host
     anyway, adding this calculation doesn't significantly increase
     your compute footprint.

     You *can* do that on the FPGA as well, but I'm not the best
     person to advise on how to do that.

         I hope you can enlighten me with your answers.

         Kind regards,

         Ghassan

         *Ghassan Ameer*

         Networks and Systems

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         *Satellite Applications Catapult Ltd*

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 be free from viruses but the Satellite Applications Catapult
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