Hi

I would assume that either the 20 or 60 MHz is already a square wave. If they both are, use the 20, if not use
which ever one is a square wave already.

Past that it is just a divide by 2 or a divide by 3 followed by a divide by 2. You want the last stage to be divide
by 2 so the output is symmetrical.

One of a multitude of possible divide by 3 circuits:

http://www.indiabix.com/electronics-circuits/divide-by-3/

The divide by 2 would just be a D F-F with the inverted output tied to the D input.

I would build it out of whatever fast modern logic is available. My preference would be for a +5 supply coming
off of something like an LT1763 linear regulator. Buffers up the outputs with several inverters in parallel.

Yes it’s not the ultimate super duper circuit. Done properly it will be about 100X lower noise than your
Rb at Tau <= 10 seconds.

Bob

Bob:

The output of the 60 and 20 MHz are sine waves. The 60MHz is very clean whereas the 20Mhz is not. The ebay link has picture of the outputs and they mirror my results. Thanks for the tip on the LT1763, probably better to use a modified schematic of the one I posted and modify the circuit as I don't need all the dividers, but it has the circuitry for the amplifiers and buffers as well "wave shaping" the input.

Cheers

-=Bryan=-

Hi

Take a look at how the 60 MHz is generated. I believe that you will find that you have a sine wave that has come out of a logic gate via a low
pass filter or that they square it up on the board already.

My guess is that you could fit a little board with a divide by 6 into the Rb and run it off of the device’s internal supplies. You would then have
a 10 MHz unit.

Bob

On 4/26/2015 3:51 AM, Bryan _ wrote:

I was looking at the project from David partridges web site
http://www.perdrix.co.uk/FrequencyDivider/index.html

This is a comparator based circuit.  This will give
you worse performance than just about anything else,
but it may be good enough anyway.

Rick Karlquist N6RK

The Phase noise floor (~-143dBc/Hz @ 1kHz) of the 10MHz output of that divider is about 17dBc/Hz higher than either the LTC6957-4 (demo board) or the Holzworth HX2410 (both ~ -160dBc/Hz @ 1kHz).All measured with a 10MHz +14dBm input signal.For offsets below a few Hz shielding of the circuitry from air currents and reducing temperature fluctuations experienced by the circuitry is essential for accurate phase noise measurements.

Bruce

 On Wednesday, 6 May 2015 2:36 PM, Richard (Rick) Karlquist <richard@karlquist.com> wrote:

On 4/26/2015 3:51 AM, Bryan _ wrote:

  I was looking at the project from David partridges web site
http://www.perdrix.co.uk/FrequencyDivider/index.html

This is a comparator based circuit.  This will give
you worse performance than just about anything else,
but it may be good enough anyway.

Rick Karlquist N6RK

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and follow the instructions there.

Hi Rick:

Any suggestions for a circuit with better performance. Purpose will be a external standard for a frequency counter.

-=Bryan=-

That's one of the reasons I was considering a re-spin of the board using a "better" ZCD solution.

Dave
-----Original Message-----
From: time-nuts [mailto:time-nuts-bounces@febo.com] On Behalf Of Richard (Rick) Karlquist
Sent: 05 May 2015 05:10
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] Divider circuit for Rubidium Standard

Rick Karlquist N6RK

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and follow the instructions there.

Wenzel has published the schematic of an excellent squaring circuit.  I
don't have the URL for their version handy, but I used it (with a couple
of mods) in the TADD-2 and TADD-2 Mini designs.  You can see the
schematic in the T2-Mini users guide at
http://www.tapr.org/~n8ur/T2_Mini_Manual.pdf.

It will square up signals as low as -20dBm with very low jitter, and
provides a TTL-compatible output.

John

On 5/6/2015 2:52 AM, Bryan _ wrote:

Hi

A standard input on a frequency counter is not a very demanding thing in the hierarchy of
TimeNut signals. You can drive any of them with some pretty simple logic gate based
circuits. No need to spend a lot of money.

Bob

On 5/6/2015 3:24 PM, Bob Camp wrote:

Logic gate, yes.  Comparator, no.

Rick

On Wed, 06 May 2015 18:09:03 -0700
"Richard (Rick) Karlquist" richard@karlquist.com wrote:

This reminds me a lot of a similar discussion a couple of weeks ago.
(where the issue boiled down to noise bandwidth)

What is the problem with a comparator vs a logic gate?
What makes the logic gate supperior?

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

Hi

I guess the simple answer is “when you measure them that’s the result”.

The slightly more complex answer is “fast silicon CMOS is indeed good, other
types may require further analysis”.  In general the faster stuff is better than
the slower CMOS.

Deeper into it you get to the fact that the gate is optimized for one input swing range,
speed and consistent (short) delay. The amount of time that anything in a CMOS gate spends
in-between “on” and “off” if very short. If you look at the time it’s hooked to a rail as noiseless (=
quiet supplies), then the time noise can get into the output is quite short. Short time = little noise.

You could go further with fancy tools.

Bob

Hi Bob:

i assume when you are referring to the comparator you are referencing the ADCMP600 or MAX999 that is used to clock shape the input for the logic dividers etc and the 74AC541 bus drivers.

Could one modify the circuit to use a low noise LTC6957 to clock shape and then divide down using the existing circuitry. I would assume this would offer a greater improvement in phase noise?

Cheers

-=Bryan=-

Hi

The simple answer is that pumping the sine wave into a biased logic gate works down
to at least the 2x10^-13 (at 1 second tau) level.

Why spend more than 10 cents when you don’t have to ?

Bob

On 5/8/2015 2:19 PM, Bob Camp wrote:

The comparator as a squarer circuit is folklore that unsophisticated
users want to believe in, because it is seemingly the easiest way
to get the job done.  Wouldn't it be wonderful to be able to put in
any signal from -30 dBm to +15 dBm and get a perfect square wave
out with no effort?  Unfortunately, what a comparator looks like
is a very high gain differential amplifier that is slew rate limited.
The threshold voltage input must be extremely low noise or it
will introduce jitter.  Even if the input pin is clean, there is
internal noise.  Driving it will a low level signal will produce
a jittery output for obvious reasons.  The trouble is that if you
drive it with a high level signal, the jitter doesn't go away because
the input stage is already in saturation.  Also, the effective noise
figure of the comparator is usually high.  Making the comparator
faster exacerbates the problem.  Read papers on "zero crossing
detectors" such as John Dick's 1990 paper in PTTI and you will
see that a comparator is the exact opposite architecture from
the optimum one.  I hope that clears up the question.

Regarding logic gates:  it is not so much that there is something
magic about gates; actually ECL gates are lousy.  It is just that
comparators are so bad that almost anything else is better.

Rick Karlquist N6RK

Hi

The only gates that seem to do very well are high speed (as in 74AC or faster)
silicon CMOS. You need to run them with a fairly clean supply and feed them
with a p-p input that matches the supply voltage. Other than that, not a lot
of magic. Are they ideal - surely not. Will they hit 2x10^-13 ADEV at 1 second and
drop from there as tau increases - yes they will.

Bob

Interesting.  Back in the stone age in 1990, 74AC was state of the art.
As soon as it came out, I used it exclusively for everything that didn't
require ECL, for which I used ECLinPS exclusively.

In the 5071A, we used one to square up 80 MHz for the DDS board.  You
are exactly right:  put in a huge sinewave obtained by good old
fashioned analog anplifiers and let the 74AC do its thing.  80 MHz
is pretty much flat out for a 74AC series. The 80 MHz came from a
10 to 80 MHz multiplier running from the 10811.

Rick Karlquist N6RK

Rick,

On 05/20/2015 01:10 AM, Richard (Rick) Karlquist wrote:

The older HP counter manuals explained it very nicely too, as they
illustrated the slew-rate & amplitude noise to time-noise conversion.

What do amazes me is the fact that I've yet to see a counter input
channel which takes care to square up the signal properly, they rather
provide the comparator after the obvious damping and AC-blocking
conditioning. I can't even recall that there where much such shaping as
a side-product.

Now, remind me why ECL is lousy, I can't recall there being very high
gain in them, but fairly high bandwidth and they stay in the linear
operation region.

PS. Sniffed the heat from a 1979 ECL based PM6674 counter as I was doing
some checkout before put it in the hands of a friend.

Cheers,
Magnus

HI

… you actually can do a pretty good job with just a terminated L network feeding the input
to the gate. It’s a high input impedance so driving it from 200 to 1K ohms isn’t all that
different than 50 ohms. Again - not ideal, but it saves a few parts and some current.

Bob

On 5/20/2015 11:22 AM, Magnus Danielson wrote:

The counter front ends seem to be modeled after scope front ends
and scope triggering circuits, where you can adjust the triggering
level.  Any jitter in the triggering would normally only affect
the interpolator.  The interpolators in general were no great shakes,
so the triggering wasn't the limiting factor.

ECL is bad because the voltage swing is low; because as you say,
a lot of the circuitry is in the active region all the time, and
because the current source in the emitters generates a lot of
noise.

In the early 1990's, I thought I had proved that the high ECL
noise was mostly common mode and that you could reduce it
20 dB by using a transformer to couple the output.  Alternately,
a good differential amplifier with high CMRR would do the trick.
I had actual measurements to back up this theory.

Subsequently, other people tried to reproduce this and could not.
By that time, I had moved on and didn't have the bandwidth to
continue to own the problem.

It would make a nice project for some time-nut to prove or disprove
my hypothesis regarding ECL.

ECL line receivers as squarers are not as bad as comparators, but
are much noisier than 74AC.

Rick Karlquist N6RK

Rick Karlquist N6RK

once upon the time at Gigatronics we compared logic devices noise and
found that  TTL were the quietest
73
KJ6UHN Alex

On 5/20/2015 3:15 PM, Richard (Rick) Karlquist wrote:

Hi

Before the 74AC stuff came along, some flavor of TTL was the best bet. With TTL you needed to be a bit
carefull about just what family (and in some cases manufacturer) you used. All that picky stuff has pretty much
gone away with fast silicon CMOS, at least among the major outfits.

Bob

On 05/21/2015 12:15 AM, Richard (Rick) Karlquist wrote:

Depends on the signal.

Yes, it is bound to have 1/f noise with it's 50 Ohm current load.
I was thinking about the continuous current, as I do know of the gating
effect. Today there is other interface standards having lower swings
than ECL.

Interesting.

Don't have a lot of ECL lying around, but some toys that might measure
things.

Cheers,
Magnus

Am 21.05.2015 um 23:32 schrieb Magnus Danielson:

Could we agree on a test procedure?

A friend of mine did some tests for synthesizers in mil. avionics and he
told me
that Motorola's MOSAIC3 process was the worst thing that has hit the
planet wrt
phase noise. That was used for a lot of fast ECL. (Some years have
passed since
he made the test.)

Comparators have their advantages, too. At least, someone has been thinking
about dispersion, constant flowthrough time against frequency and
overdrive;
there are even specs that include overdrive. Just that comparators can
switch
cleanly at mV levels does not mean that they are to be used that way.

More gain may mean more noise voltage, but it also means less time spent
in the transition region. Once the decision has been made the noise is
squelched
anyway.  And I prefer setting the bandwidth with thin film Rs and np0
capacitors,
not with oversized junctions.

The fairest shootout between the logic families that we have is the LTC6957.

< http://cds.linear.com/docs/en/datasheet/6957f.pdf >

Probably just bondout options of the same chip. The PECL version wins
hands-down, LVDS is worst and CMOS is in-between.

Especially at low offsets PECL is best, that clearly contradicts the
above-assumed 1/f problem and the lower swing standard of today
comes out worst.

regards, Gerhard

Hi

The way I’ve tested most of this is with a TimePod or something similar. You start with
a power splitter of some sort (active or passive) and feed one input to the tester off of one port. The DUT
connects to the other port. Once the signal has flowed through what ever circuits you
have, it’s output goes to the other input of the tester.

In the “good old days” the test had to be done with two pieces of gear. You ran one set
of tests with a short term stability box. You ran another set of tests with a phase noise
analyzer. The nice thing about the more modern gear is that you can run both tests
at once. That’s nice when you consider that the tests run for > 10 hours  in many cases.

If you want to go really old school, you can run a single mixer setup for the phase noise
and a DMTD for the short term. That approach works (been there done that). You do
need to start by testing some amplifiers.

I’ve found that the results make more sense if you use a good signal source for the testing.
An OCXO is generally a good idea. If you have a source with a lot of AM noise, you will spend
time learning about AM to PM conversion …

What to expect:

Phase noise @ 100KHz can / might get down below -190 dbc Hz. Short term can / might
hit 1x10^-14 at 1 second. You will need some pretty good setups to get that data. The bad
news is that those numbers are not the bottom of the range :)

You probably will spend some time checking things like square to sine converters. In some
cases they will be pretty easy in others they will turn out to tell you a lot about how your HVAC
system is running overnight.

Bob

On Friday, May 22, 2015 10:48:16 AM Gerhard Hoffmann wrote:

measure

thinking

spent

LTC6957.

The LT6957 dtasheet PN curves differ from what I measured with a 10-MHz
input in that when shielded from air currents the flicker noise corner is
much lower than 100Hz offr a 100MHz input.
I have only tested the LTC6957-4 evaluation board.

Bruce

set shown fo

After reading the posts on this subject I have a question.
First, in my experience I used a rather simple circuit made from
diodes used as limiters and a transistor feeding
a logic inverter. No AGC.

So here is my question. What is the proper circuit to use?
I'd like to do a PSPICE and check things out followed by
a prototype.

I got that a comparator is out, etc.

Cheers,
George H. N2FGX

On 04/26/2015 06:51 AM, Bryan _ wrote:

Hi

What is your objective? Put another way:

1. How clean is your sine wave source?
2. What frequency (or range) are you trying to convert?
3. What level range are you trying to work with?
4. What is it going into (how clean is the next stage)?

If you have an optical fountain that is good to 1x10^-15 at 1 second, and
you are trying to map Pluto with a radar in your back yard, the answer will
be a bit different than if you are starting with a surplus OCXO and trying
to drive a 5334 :)

Bob

Bob,

This are all great questions.

1. Let's assume that it varies from a HP Signal generator
   to a home built device. However, If I was to build it I
   would expect to pay more and get better specs.
   I have a few HP 3325B's and a few 8660C.
   I would probably use those as inputs but not always.

2. Let's stick with the basics: 5-10Mhz.

3. Again, basics: 1-7V peak to Peak.

4. Ok, this is the real important question.
   The answer is, an amplifier of some sort.
   And that amp will probably feed something
   like a Test Instrument or some circuit I
   am building. What are my options?

For now, I'd like to simulate some of my simple
designs as well as some designs suggested here.
Then, see where it goes.

George

On 05/22/2015 05:31 PM, Bob Camp wrote: