Hi

The simple answer is that a biased fast CMOS gate will do a better job
ADEV wise than your signal sources will. If you want that to also hold
for phase noise, run the gate on 5.5V and get the input signal as close to that
(5.5V p-p) as you can.

Bob

Hi

To answer the next part of the question - simulation:

Noise wise, Spice is fundamentally a linear analysis program. Logic gates
mostly operate in a non-linear fashion (full on / full off). The noise
models that are commonly used (when you can even find them)
apply to fairly limited “active region” conditions.

In this case, you have noise in the “DC” region and at audio modulating
your signal. It’s very much a non-linear case. A conventional Spice
analysis will quickly lead you astray. You can make it work after
the fact by plugging this and that in here and there. To do that, you
need to measure some parts and then back fit the dummy elements
in the model to your results.

To predictively accurately model noise in a gate as it switches  you need:

1. A program that handles non-linear models properly
2. The basic device models for the devices in your IC
3. The non-linear noise add-on for your analysis program
4. The generalized non-linear noise models (DC to GHz) to add onto your device data
5. A way to convert the result into something meaningful (ADEV , phase noise)

Last time I looked, 1 + 3 ran above $125K for something that might be accurate. The
models for the IC process devices (2 above) were “sort of” included in that price.
Adding 4 to the mix was a “cost plus” sort of thing. Obviously number 5 is a
“do it your self” task.

Far cheaper (at least 10X) to just build one and buy all the brand new gear needed to test it.
We’re not talking about big buckets of noise, this stuff is all mighty far down. 1x10^-14 is a
long long ways. A simple term like “accurate” gets a major workout in this case. If once
you have your data, you want to back fit a dummy model - go for it.

Bob

Bob wrote:

Maybe or maybe not, at tau ~1 second.  Trouble is, as tau gets
larger, the gate performs worse.  The switching threshold of all
MOSFET logic devices varies all over the place with temperature and
supply voltage as well as random drift.  At tau >10 or 100 seconds,
these effects become more and more pronounced and xDEV gets worse,
even if you take pains to keep the circuitry out of drafts.  Gates
are not a good way to square sine waves if you care about stability
at longer tau.

Most of what has been said against comparators on this thread are
indictments of mistakes made in applying them, NOT deficiencies of
comparators per se.  I don't have the time nor energy to go into it
in any depth right now, but: Properly applied, comparators can work
better than pretty much anything else when the job is squaring a 1 to
100 MHz sine wave.

A few "Do's" and "Do not's":

Do use a comparator with split supplies for the input section, so you
can use actual ground as the reference voltage.  Do not use inputs
biased to mid-supply.  Most especially, do not use separate voltage
dividers to bias the two inputs, because the divider noise is
uncorrelated and adds.  If you must use inputs biased to mid-supply,
use one good, low-noise voltage reference (LM329 or LM399) to bias
both inputs so the bias noise is low and is common-mode (make sure to
keep the time constants equal at the two inputs).  But just don't use
inputs biased to mid-supply in the first place.

Do use a comparator with properly-designed internal hysteresis of a
few mV (e.g., LT1719).  Do use a good, modern comparator (again,
e.g., LT1719) that was designed since chip-level thermal flow
analysis became standard practice, to avoid the mysterious drift,
instabilities, and metastabilities that comparators from the bad old
days (mid-'90s and earlier) were famous for.

Do not rely on a comparator to work with inputs from mV to 10s of
volts.  You wouldn't expect that with a logic gate, why in the world
would you expect it with a comparator?  Adjust the input level with
amplifiers or attenuators to the optimum value for the comparator you
are using at the frequency you are operating.

A 5 or 10Vp-p sine wave at 10MHz slews fast enough at zero-cross not
to need bandwidth-limited clipping amplifiers (a la Dick and
Collins).  Those techniques were designed for squaring
audio-frequency sine waves, such as the mixer output(s) of a single-
or double-mixer system.  If you feel the need, you can increase the
zero-crossing slope of the input signal by starting with a larger
input signal than is optimum for the comparator in use and using
diode clamps to limit the peak amplitude.

There are many other best practices, but the ones above are enough to
avoid the major application mistakes and have a reasonable chance of
designing something that works to a high standard.

Best regards,

Charles

I was the OP and the reason for the whole exercise is to take a Rubidium standard that only outputs 1pps and modify for use as 10MHz. With some research there is a 20Mhz source onboard, issue is the sine is not very clean at 20MHz (60MHZ as well, much cleaner and may be worth inputting straight to logic). Thus the need for a divider circuit to divide down to 10Mhz. The purpose is to create a bench standard for hobby use and a external 10MHz reference for a HP 53131A

Pics of the waveforms (not my pics but my results are the same)

http://1drv.ms/1HB0Nwn

-=Bryan=-

Hi

Yes indeed, if you have a clock that goes below 1x10^-15 at 1 second and drops linearly with tau from there, you will have issues. If you do not have such a clock. The gate probably will do just fine.

The delta on the gate turns out to be a delta time (as in delta ns / ps / fs). As you go out in tau, the impact (parts in 10^whatever) of that time delta drops linearly with tau.

So: what sort of clock (that you have) are you proposing to look at?

Bob

Moin John,

Yes, I know I am comming back to an "old" discussion, but I have questions
that need to be answered! :-)

On Wed, 06 May 2015 08:56:10 -0400
John Ackermann N8UR jra@febo.com wrote:

The manual says:
---schnipp---
The purpose of the input circuit is to convert the RF input signal
into a low-jitter square wave that can drive the PIC clock input.
The circuit is closely based on the one published by Wenzel at
http://www.wenzel.com/documents/waveform.html, with modifications
suggested by Bruce Griffiths and Ulrich Bangert. The revised circuit
works with inputs as low as -20dBm.
---schnapp---

The modification I can see is that the "current source" part of the
differential pair changed from being a single, shared resistor of 100R to
an inductor of 100uH, then splits up into two resistors of 220R,
which are bridged by a 100nF capacitor. The inductor results in a
reactance between 62R (100kHz) and 12k (20MHz) for the input range.

Can you shed a bit of light on why you did those modifications
and what the intended effect is?

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

Splitting the resistor in 2 and ac coupling the emitters together reduces the effects of Vbe and/or base biasing mismatch allowing a more symmetric output and/or operation at lower input signal levels.The inductor reduces the high frequency variations in the total emitter current. It also reduces the tail current noise at high frequencies.
Bruce

On Sunday, 10 January 2016 10:05 AM, Attila Kinali <attila@kinali.ch> wrote:

Moin John,

Yes, I know I am comming back to an "old" discussion, but I have questions
that need to be answered! :-)

On Wed, 06 May 2015 08:56:10 -0400
John Ackermann N8UR jra@febo.com wrote:

The manual says:
---schnipp---
The purpose of the input circuit is to convert the RF input signal
into a low-jitter square wave that can drive the PIC clock input.
The circuit is closely based on the one published by Wenzel at
http://www.wenzel.com/documents/waveform.html, with modifications
suggested by Bruce Griffiths and Ulrich Bangert. The revised circuit
works with inputs as low as -20dBm.
---schnapp---

The modification I can see is that the "current source" part of the
differential pair changed from being a single, shared resistor of 100R to
an inductor of 100uH, then splits up into two resistors of 220R,
which are bridged by a 100nF capacitor. The inductor results in a
reactance between 62R (100kHz) and 12k (20MHz) for the input range.

Can you shed a bit of light on why you did those modifications
and what the intended effect is?

            Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
                -- Miss Matheson, The Diamond Age, Neil Stephenson

time-nuts mailing list -- time-nuts@febo.com
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and follow the instructions there.

On 1/9/2016 12:44 PM, Attila Kinali wrote:

This circuit is very similar to one that was championed by Tom
Faulker of HP/Agilent at the now closed Spokane site.  Tom
measured the circuit at about -171 dBc/Hz.  He was very knowledgeable
about this topic, so we can believe the number.

This is good, because the cited Wenzel document would give me
no confidence whatsoever if that was all I had to go on.  It
reads like it was written by some marketing guy (as opposed to
R&D) who knows just enough to be dangerous.  Other than the
circuit in question, the rest of the document is full of
unreliable information.  Such as how line receivers make great
sine wave to square wave converters.  They are terribly noisy.
IE, the document contains a kernel of truth.  It also has no
quantitative information about the circuit in question or
any other ones discussed.  It's disappointing to see this
published by an otherwise excellent outfit like Wenzel.

The modifications make sense IMHO.  I suspect that the 2N3906's
are good for two reasons:  the low f-t reduces noise bandwidth
and the high current gain reduces noise current.

Rick Karlquist N6RK

Moin Bruce,

On Sat, 9 Jan 2016 21:36:35 +0000 (UTC)
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:

Thanks for the explanation!

One additional question: Why is the bias voltage for the two transistors
derived independently? In my naivite i would have used a single resistive
devider, buffered it with a large enough C and then split that bias voltage
off with a 3.3k resistor each. This would get rid off the bias mismatch.
(though not of the mismatch of the transistors)

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson

Hi Rick,

On Sat, 9 Jan 2016 14:45:43 -0800
"Richard (Rick) Karlquist" richard@karlquist.com wrote:

Is this documented anywhere publicly? I would be very interested
to read this.

		Attila Kinali

--
It is upon moral qualities that a society is ultimately founded. All
the prosperity and technological sophistication in the world is of no
use without that foundation.
-- Miss Matheson, The Diamond Age, Neil Stephenson