Re: [time-nuts] yet another GPSDO design, or so
Attilia
What you want is basically a Shera Board. That design has been around for
quite some time and has served me very well. I have a total of six running
including two controlling Rubidium. There are in my opinion a couple of
problems: not every 4066 works on the design the 18 bit D/A is very hard to
find and now expensive and the single step of the D/A is intended for a 1.7
E-13 frequency step. I have build a input section that counts 100 MHz in
stead of 24 MHZ making the unit create steps of 4.3 E-14 which works better on
my Rubidium's and Datum FTS 1000. Also it eliminates the 4066's. Since I
do not know how to write code that was my solution. I have also designed a
later version Shera, with less IC's and a low cost dual D/A but I do not
have the programming skill.
If you contact me directly I will send you a copy of the QST Shera article,
my design and the D/A data sheet.. I am sure you can replace the PIC with
an Atmel device.
In a message dated 6/26/2010 1:16:09 P.M. Eastern Daylight Time,
attila@kinali.ch writes:
Moin,
I recently had a look at the data sheet of the LEA6-T GPS module
from ublox, which now features a second time pulse output that
is capable of delivering a 10MHz signal, synchronized to GPS.
After thinking quite some time quite some time about building
my own GPSDO and struggling with the question how to synchronize
a 10MHz signal to a 1Hz signal that has some substantial phase
noise, the new LEA6-T module seems like to make things a lot
easier. Although the LEA6 specs do not say anything about how
the timepulse output is generated or how it is synchronized
to GPS, i assume that it will either have some jumps or phase/frequency
noise due to oszillator and synchronization imperfections.
But, it should be possible to use the LEA6-T together with
some OCXO and a PLL setup to stabilize the OCXO to get a high
quality frequency standard.
Unfortunately, my knowledge in that field is rather limited, thus
before starting to make wrong design decisions i'd like to ask
for some advice here.
My basic idea is to feed the 10MHz output of the LEA6-T and
the 10MHz OCXO into a current output PFD, do some low-order
filtering of the output signal. Feed that into an ADC which
is read by a uC which in turn controls an DAC that sets over
some amplifier stage the EFC input of the OCXO.
As PFD i thought about using a ADF4002 from Analog, which
is actually an PLL, but allows to bypass the input dividers,
so that it can be used as pure current output PFD.
I'm not yet sure what kind of output filter i want to use.
I probably have to add at least one low noise opamp there,
to isolate the PFD output/filter from the ADC. I'm also
not sure what filter frequency i should use here. It will
have to be below 10MHz for sure, probably in the lower
kHz range, but how low is the question. The lower the easier
gets the ADC stage and the less work has to be done in the uC,
but using a low frequency filter either means using an active
filter (noise) or high value R or L (again noise, especially
the L might couple in 50Hz noise from the enviroment or show
microphone effects).
The ADC will be either a low-noise 16bit type or a 24bit
type. This will largely depend on the sample rate to be
used and the availabilty of the ADCs. Any good advices
on what to use here? Should there be some form of signal
conditioning done? If, what form of conditioning would
you advise me to use?
As a uC i thought about using a AT91SAM7 variant from Atmel.
I know these beasts (and their bugs) pretty well by now
and already have some code ready for those.
I thought about clocking the uC with a 40MHz crystal that
is synchronized to the 10MHz OCXO using a PLL. This would
allow me to generate quite precise+accurate digital signals.
Unfortunately, there doesnt seem to be VCXOs at 40MHz available
so that means that i'd have to build one by hand.
The loopfilter is going to end up in the uC as it is easier
to build such low frequency filters digitally than in analog.
I havent put much thought into how that filter should look
like, as this can be easily changed later.
The DAC will probably be a 16bit type (there does not seem
any higher resolution DAC with sane specs and still reasonable
availability). The amplifier for the DAC output will be a two
stage amplifier. One stage that adds an (adjustable) offset
and one stage that adds the (again adjustable) amplification.
This approach is choosen as the needed EFC range will probably
much lower than the full range. Hence the resolution of the
DAC can be enhanced by producing only values within that range.
The disadvantage here is that it requires calibration.
A rough guestimate is that the whole thing will probably cost
less than 500CHF (including PCB production, but excluding OCXO).
Yes, i know, i could get a Rb frequency standard for that money
on ebay. But where is the fun in that? ;-)
Beside whether this setup makes sense, the two biggest questions
i have are, what OCXO to use. Are the ISOTEMP 134-10 that are
available on ebay "good enough" for such an application?
Or shall i look for something better/different?
And the other is, how do i amplify and distribute the 10MHz
signal i get out of the OCXO to be used by other devices
with minimal phase noise?
Thanks for your help
Attila Kinali
--
If you want to walk fast, walk alone.
If you want to walk far, walk together.
-- African proverb
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
I have been thinking about a faster counter also but the Shera board was depending on the jitter in the 24 Mhz clock to average out the +- count. The faster clock would reduce the need for this but without the right amount of jitter we lose the benefit of this average.
Stanley
----- Original Message ----
From: "EWKehren@aol.com" EWKehren@aol.com
To: time-nuts@febo.com
Sent: Sat, June 26, 2010 8:14:02 PM
Subject: Re: [time-nuts] yet another GPSDO design, or so
Attilia
What you want is basically a Shera Board. That design has been around for
quite some time and has served me very well. I have a total of six running
including two controlling Rubidium. There are in my opinion a couple of
problems: not every 4066 works on the design the 18 bit D/A is very hard to
find and now expensive and the single step of the D/A is intended for a 1.7
E-13 frequency step. I have build a input section that counts 100 MHz in
stead of 24 MHZ making the unit create steps of 4.3 E-14 which works better on
my Rubidium's and Datum FTS 1000. Also it eliminates the 4066's. Since I
do not know how to write code that was my solution. I have also designed a
later version Shera, with less IC's and a low cost dual D/A but I do not
have the programming skill.
If you contact me directly I will send you a copy of the QST Shera article,
my design and the D/A data sheet.. I am sure you can replace the PIC with
an Atmel device.
In a message dated 6/26/2010 1:16:09 P.M. Eastern Daylight Time,
attila@kinali.ch writes:
Moin,
I recently had a look at the data sheet of the LEA6-T GPS module
from ublox, which now features a second time pulse output that
is capable of delivering a 10MHz signal, synchronized to GPS.
After thinking quite some time quite some time about building
my own GPSDO and struggling with the question how to synchronize
a 10MHz signal to a 1Hz signal that has some substantial phase
noise, the new LEA6-T module seems like to make things a lot
easier. Although the LEA6 specs do not say anything about how
the timepulse output is generated or how it is synchronized
to GPS, i assume that it will either have some jumps or phase/frequency
noise due to oszillator and synchronization imperfections.
But, it should be possible to use the LEA6-T together with
some OCXO and a PLL setup to stabilize the OCXO to get a high
quality frequency standard.
Unfortunately, my knowledge in that field is rather limited, thus
before starting to make wrong design decisions i'd like to ask
for some advice here.
My basic idea is to feed the 10MHz output of the LEA6-T and
the 10MHz OCXO into a current output PFD, do some low-order
filtering of the output signal. Feed that into an ADC which
is read by a uC which in turn controls an DAC that sets over
some amplifier stage the EFC input of the OCXO.
As PFD i thought about using a ADF4002 from Analog, which
is actually an PLL, but allows to bypass the input dividers,
so that it can be used as pure current output PFD.
I'm not yet sure what kind of output filter i want to use.
I probably have to add at least one low noise opamp there,
to isolate the PFD output/filter from the ADC. I'm also
not sure what filter frequency i should use here. It will
have to be below 10MHz for sure, probably in the lower
kHz range, but how low is the question. The lower the easier
gets the ADC stage and the less work has to be done in the uC,
but using a low frequency filter either means using an active
filter (noise) or high value R or L (again noise, especially
the L might couple in 50Hz noise from the enviroment or show
microphone effects).
The ADC will be either a low-noise 16bit type or a 24bit
type. This will largely depend on the sample rate to be
used and the availabilty of the ADCs. Any good advices
on what to use here? Should there be some form of signal
conditioning done? If, what form of conditioning would
you advise me to use?
As a uC i thought about using a AT91SAM7 variant from Atmel.
I know these beasts (and their bugs) pretty well by now
and already have some code ready for those.
I thought about clocking the uC with a 40MHz crystal that
is synchronized to the 10MHz OCXO using a PLL. This would
allow me to generate quite precise+accurate digital signals.
Unfortunately, there doesnt seem to be VCXOs at 40MHz available
so that means that i'd have to build one by hand.
The loopfilter is going to end up in the uC as it is easier
to build such low frequency filters digitally than in analog.
I havent put much thought into how that filter should look
like, as this can be easily changed later.
The DAC will probably be a 16bit type (there does not seem
any higher resolution DAC with sane specs and still reasonable
availability). The amplifier for the DAC output will be a two
stage amplifier. One stage that adds an (adjustable) offset
and one stage that adds the (again adjustable) amplification.
This approach is choosen as the needed EFC range will probably
much lower than the full range. Hence the resolution of the
DAC can be enhanced by producing only values within that range.
The disadvantage here is that it requires calibration.
A rough guestimate is that the whole thing will probably cost
less than 500CHF (including PCB production, but excluding OCXO).
Yes, i know, i could get a Rb frequency standard for that money
on ebay. But where is the fun in that? ;-)
Beside whether this setup makes sense, the two biggest questions
i have are, what OCXO to use. Are the ISOTEMP 134-10 that are
available on ebay "good enough" for such an application?
Or shall i look for something better/different?
And the other is, how do i amplify and distribute the 10MHz
signal i get out of the OCXO to be used by other devices
with minimal phase noise?
Thanks for your help
Attila Kinali
--
If you want to walk fast, walk alone.
If you want to walk far, walk together.
-- African proverb
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Moin,
On Sat, 26 Jun 2010 21:14:02 EDT
EWKehren@aol.com wrote:
What you want is basically a Shera Board. That design has been around for
quite some time and has served me very well.
Yes. The Shera Board and similar designs serve as an example for me.
I have a total of six running
including two controlling Rubidium. There are in my opinion a couple of
problems: not every 4066 works on the design the 18 bit D/A is very hard to
find and now expensive and the single step of the D/A is intended for a 1.7
E-13 frequency step.
Yes. My goal is to update the venerable 4066 with something more
modern and have components that are easy to get trough farnell, digikey,
mouser, and all the other distributors. Yes, 16bit D/A seems to
be the maximum that is currently available. It crossed my mind
to build a 24bit R-2R D/A using discrete components, but this might
have actually a worse performance than a off the shelf 16bit D/A.
(temperature drifft, resistor values missmatch, EMI, etc)
Attila Kinali
--
If you want to walk fast, walk alone.
If you want to walk far, walk together.
-- African proverb
Attila Kinali wrote:
Moin,
On Sat, 26 Jun 2010 21:14:02 EDT
EWKehren@aol.com wrote:
What you want is basically a Shera Board. That design has been around for
quite some time and has served me very well.
Yes. The Shera Board and similar designs serve as an example for me.
I have a total of six running
including two controlling Rubidium. There are in my opinion a couple of
problems: not every 4066 works on the design the 18 bit D/A is very hard to
find and now expensive and the single step of the D/A is intended for a 1.7
E-13 frequency step.
Yes. My goal is to update the venerable 4066 with something more
modern and have components that are easy to get trough farnell, digikey,
mouser, and all the other distributors. Yes, 16bit D/A seems to
be the maximum that is currently available. It crossed my mind
to build a 24bit R-2R D/A using discrete components, but this might
have actually a worse performance than a off the shelf 16bit D/A.
(temperature drifft, resistor values missmatch, EMI, etc)
Attila Kinali
Its possible to build a 24 bit resolution D/A using a synchronously
filtered PWM circuit.
A pair of PWM outputs and a few relatively low precision resistors and
capacitors together with a low noise low drift reference are required.
The technique takes advantage of the fact that the required EFC voltage
changes slowly and isnt updated at a highg rate.
The synchronous filter technique eliminates the very long time constant
RC filters required with an asynchronously filtered PWM waveform.
Bruce
Bruce Griffiths wrote:
Attila Kinali wrote:
Moin,
On Sat, 26 Jun 2010 21:14:02 EDT
EWKehren@aol.com wrote:
What you want is basically a Shera Board. That design has been around
for
quite some time and has served me very well.
Yes. The Shera Board and similar designs serve as an example for me.
I have a total of six running
including two controlling Rubidium. There are in my opinion a couple of
problems: not every 4066 works on the design the 18 bit D/A is very
hard to
find and now expensive and the single step of the D/A is intended
for a 1.7
E-13 frequency step.
Yes. My goal is to update the venerable 4066 with something more
modern and have components that are easy to get trough farnell, digikey,
mouser, and all the other distributors. Yes, 16bit D/A seems to
be the maximum that is currently available. It crossed my mind
to build a 24bit R-2R D/A using discrete components, but this might
have actually a worse performance than a off the shelf 16bit D/A.
(temperature drifft, resistor values missmatch, EMI, etc)
Attila Kinali
Its possible to build a 24 bit resolution D/A using a synchronously
filtered PWM circuit.
or with a pair of current output DACs and a resistive divider/summer so
you have a "high order" and "low order" voltage.
On Tue, 29 Jun 2010 21:32:10 +1200
Bruce Griffiths bruce.griffiths@xtra.co.nz wrote:
Its possible to build a 24 bit resolution D/A using a synchronously
filtered PWM circuit.
A pair of PWM outputs and a few relatively low precision resistors and
capacitors together with a low noise low drift reference are required.
The technique takes advantage of the fact that the required EFC voltage
changes slowly and isnt updated at a highg rate.
The synchronous filter technique eliminates the very long time constant
RC filters required with an asynchronously filtered PWM waveform.
I've thought about that, but i'm afraid that this will add too
much phase noise trough EFC noise. Though, i have not calculated
how much noise this would generate.
Attila Kinali
--
If you want to walk fast, walk alone.
If you want to walk far, walk together.
-- African proverb
Hi
Summing a pair of DAC's and checking them with an ADC is one way to get the
job done. It's been used quite a bit.
16 bit DAC's are sub $3 items these days with pretty good specs on the
parts. A multi channel <1 ppm accurate 24 bit "DC" ADC is a fairly common
part as well. Raw parts cost from Digikey for PIC and the rest of it (except
reference) likely would be sub $20. If you have all the parts already I
suppose it could be free. Even with a $50 charge for a quick turn PCB
there's not a lot being spent for the ADC side of things.
You can spend a lot on a reference. That's going to be true for any long
term stable stand alone EFC drive setup. My guess is that reference noise on
affordable parts may drive you to the big R/C's. Putting at least one
channel of the ADC after the big R/C lets you get a handle on leakage
issues.
Bob
-----Original Message-----
From: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] On
Behalf Of Bruce Griffiths
Sent: Tuesday, June 29, 2010 5:32 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] yet another GPSDO design, or so
Attila Kinali wrote:
Moin,
On Sat, 26 Jun 2010 21:14:02 EDT
EWKehren@aol.com wrote:
What you want is basically a Shera Board. That design has been around for
quite some time and has served me very well.
Yes. The Shera Board and similar designs serve as an example for me.
I have a total of six running
including two controlling Rubidium. There are in my opinion a couple of
problems: not every 4066 works on the design the 18 bit D/A is very hard
to
find and now expensive and the single step of the D/A is intended for a
1.7
E-13 frequency step.
Yes. My goal is to update the venerable 4066 with something more
modern and have components that are easy to get trough farnell, digikey,
mouser, and all the other distributors. Yes, 16bit D/A seems to
be the maximum that is currently available. It crossed my mind
to build a 24bit R-2R D/A using discrete components, but this might
have actually a worse performance than a off the shelf 16bit D/A.
(temperature drifft, resistor values missmatch, EMI, etc)
Attila Kinali
Its possible to build a 24 bit resolution D/A using a synchronously
filtered PWM circuit.
A pair of PWM outputs and a few relatively low precision resistors and
capacitors together with a low noise low drift reference are required.
The technique takes advantage of the fact that the required EFC voltage
changes slowly and isnt updated at a highg rate.
The synchronous filter technique eliminates the very long time constant
RC filters required with an asynchronously filtered PWM waveform.
Bruce
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
On 6/29/2010 11:10 AM, Attila Kinali wrote:
Yes, 16bit D/A seems to
be the maximum that is currently available. It crossed my mind
to build a 24bit R-2R D/A using discrete components, but this might
have actually a worse performance than a off the shelf 16bit D/A.
(temperature drifft, resistor values missmatch, EMI, etc)
A few years ago (circa 2004) I built a GPSDO that used the PWM feature of
an Atmel uC to generate the EFC. The PWM in that uC has only 10 bits of granularity,
but then I applied another 10 bits of dithering to the two register values
that defined the limits of the PWM. Of course, I had to low pass the generated
signal with a filter with almost 120 dB of rejection at 3.9 Hz, but this
contraption worked, and was really inexpensive, costing only a few lines of code.
Alberto I2PHD
Attila Kinali wrote:
On Tue, 29 Jun 2010 21:32:10 +1200
Bruce Griffithsbruce.griffiths@xtra.co.nz wrote:
Its possible to build a 24 bit resolution D/A using a synchronously
filtered PWM circuit.
A pair of PWM outputs and a few relatively low precision resistors and
capacitors together with a low noise low drift reference are required.
The technique takes advantage of the fact that the required EFC voltage
changes slowly and isnt updated at a highg rate.
The synchronous filter technique eliminates the very long time constant
RC filters required with an asynchronously filtered PWM waveform.
I've thought about that, but i'm afraid that this will add too
much phase noise trough EFC noise. Though, i have not calculated
how much noise this would generate.
Attila Kinali
How do you conclude that?
You don't know what the circuit is and you've never tested it.
Ulrich has, and the output noise is very low.
Bruce
Hi
Are you referring to something like this:
http://www.electronicsweekly.com/Articles/2008/05/01/43680/fast-settling-syn
chronous-pwm-dac-filter-has-almost-no.htm
as a synchronous filter for the PWM?
Bob
-----Original Message-----
From: time-nuts-bounces@febo.com [mailto:time-nuts-bounces@febo.com] On
Behalf Of Bruce Griffiths
Sent: Tuesday, June 29, 2010 4:07 PM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] yet another GPSDO design, or so
Attila Kinali wrote:
On Tue, 29 Jun 2010 21:32:10 +1200
Bruce Griffithsbruce.griffiths@xtra.co.nz wrote:
Its possible to build a 24 bit resolution D/A using a synchronously
filtered PWM circuit.
A pair of PWM outputs and a few relatively low precision resistors and
capacitors together with a low noise low drift reference are required.
The technique takes advantage of the fact that the required EFC voltage
changes slowly and isnt updated at a highg rate.
The synchronous filter technique eliminates the very long time constant
RC filters required with an asynchronously filtered PWM waveform.
I've thought about that, but i'm afraid that this will add too
much phase noise trough EFC noise. Though, i have not calculated
how much noise this would generate.
Attila Kinali
How do you conclude that?
You don't know what the circuit is and you've never tested it.
Ulrich has, and the output noise is very low.
Bruce
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.