Hi:

While reverse engineering the Quantic (then Absolute Time, then ??)
Q5200M Timing GPS receiver I came across a Stellar GPS patent that
describes how this receiver controls it's 10 MHz output using a NCO IC
as a 48 bit D/A converter.  But I have not been able to find a modern
replacement for the IC.  Is there one?

I'm also looking for the downconverter antenna.

http://www.pacificsites.com/~brooke/Q5200.shtml
U.S. patent 5440313
http://patft.uspto.gov/netacgi/nph-Parser?patentnumber=5440313
(remember that SA was on at the time of this patent.)

Have Fun,

Brooke Clarke

w/Java http://www.PRC68.com
w/o Java http://www.pacificsites.com/~brooke/PRC68COM.shtml
http://www.precisionclock.com

Rob Kimberley wrote:

On Sat, Jan 27, 2007 at 01:32:40PM +0100, Ulrich Bangert wrote:

My understanding is that that is how the PRR-10s DO work. A DDS

is used to synthesize 20 MHz from the input reference 10 MHz and a 20
MHz VCXO is locked to this DDS output and divided down to produce 1 PPS
to compare with the UT+ or M12M 1 PPS.  And the phase error data from
that comparison is used to steer the DDS.  So yes, the 20 MHz is PLL
locked to the GPS by twiddling the DDS.

I would know this much more precisely if more detailed

documentation on this now obsolete product became available (hint hint),
but since I have  several of the GPS locking boards now it may well
become worth it to get out the DMM on beep mode and start tracing etch -
and/or get out scope and logic analyzer and see what is going on...

I do admit that without schematics or reverse engineering there

are some details that are a bit fuzzy - specifically what the relative
clock domains are for the two clocks (20 MHz from the VCXO and the 10
MHz from the Rb). I suppose one can handle this two ways - use a DDS
clocked with the 20 MHz VCXO to generate a 10 MHz signal and phase
compare (at 10 MHz) this with the input 10 MHz to steer the VCXO to lock
with the Rb 10 MHz input as adjusted by the DDS NCO.  This implies that
virtually all of the logic in the board is clocked at 20 MHz by the VCXO
output, and that another channel of the primary NCO chip or a second one
can be used to generate 1 PPS slewable in phase to acquire initial lock
with the GPS 1 PPS.  In this configuration errors in the 1 PPS phase
would be use to adjust the DDS ratio so as to make it synthesize the OFF
frequency Rb reference input 10 MHz.

And the other approach is to clock the DDS NCO chip with the 10

MHz Rb reference input and use it to generate a corrected 20 MHz which
can be used to phase lock the 20 MHz VCXO.  This implies a second 10
MHz clock domain for the DDS chip and related logic from the 20 MHz VCXO
world.    The first approach strikes me as cleaner, frankly, as the
board would have one clock rather than two... and if the input clock
disappeared (very possible in this application) there would still be
clock for everything if only as good as the VCXO and not reference
quality.

--
Dave Emery N1PRE,  die@dieconsulting.com  DIE Consulting, Weston, Mass 02493
"An empty zombie mind with a forlorn barely readable weatherbeaten
'For Rent' sign still vainly flapping outside on the weed encrusted pole - in
celebration of what could have been, but wasn't and is not to be now either."

David

David I. Emery wrote:

The DDS will need to have an internal clock of at least 30MHz or so to
generate a usable 10MHz output.
A frequency multiplier, either within the DDS, or external to it is
required to generate a suitable DDS clock from either a 10MHz or 20MHz
input.
Although theoretically it is possible to generate 10MHz from a DDS
clocked at 20MHz, in practice the necessary brick wall analog
reconstruction filter is unrealisable.

Bruce

On Sun, Jan 28, 2007 at 11:43:11AM +1300, Dr Bruce Griffiths wrote:

Agreed, assuming the chip doesn't do clock multiplication as

several do...

Given my option 1 (DDS clocked at 20 mhz) and NO clock multiplication

the phase comparison with the input could easily be at say 5 mhz or 1 mhz
without degrading anything very much I shouldn't think.  Should be obvious
on a scope doing the reverse engineering of course...

Of course for phase comparison with the input, one actually does not

need much filtering as one is only using the NCO digital output as an input
to a phase comparator... spurs and so forth don't count at all here as they
get filtered out in the subsequent loop filter for the PLL (which is very
narrow).

--
Dave Emery N1PRE,  die@dieconsulting.com  DIE Consulting, Weston, Mass 02493
"An empty zombie mind with a forlorn barely readable weatherbeaten
'For Rent' sign still vainly flapping outside on the weed encrusted pole - in
celebration of what could have been, but wasn't and is not to be now either."

David I. Emery wrote:

David

I presume that the leading edge of the GPS receiver PPS pulse samples
the DDS phase accumulator register content.
This is not possible with most modern DDS chips with integrated DACs, in
which the DDS accumulator or its truncated phase output is not
externally accessible, it cannot be read, nor is there any provision for
capturing the phase at the leading edge of an external signal.

However one could always use a gate array to implement the digital part
of a DDS and include a phase capture register.
An external DAC (and sine table) would be required to synthesize the
corrected sine wave frequency source output.

Bruce

Dr Bruce Griffiths wrote:

ADDENDUM

When sampling the phase accumulator of an NCO with the leading edge of
an external signal, first the external signal must be synchronised to
the NCO clock using a multistage synchroniser. The synchroniser output
has an inherent timing jitter of about 2 clock cycles peak to peak which
limits the sampled phase effective resolution. To increase the single
shot sampled phase effective resolution, either the NCO clock frequency
can be increased, incurring greater power dissipation and cost, or a TDC
can be used to measure the synchroniser input output delay and combined
with the sampled phase to increase the effective single shot sampled
phase resolution without increasing the NCO clock frequency.

Bruce

Bruce

Dr Bruce Griffiths wrote:

David

The TDC can be eliminated if the GPS timing receiver and the DDS share
the same clock derived from the frequency reference.
The GPS receiver can then easily determine the sampled phase "sawtooth
timing error" so that the sampled DDS phase can be corrected without the
assistance of an external TDC.
Indeed if the DDS and GPS receiver were appropriately integrated then
very high resolution GPS carrier beat phase tracking techniques could be
employed to discipline the frequency standard using the DDS chip to
produce the corrected output frequency.

Bruce

On Sun, Jan 28, 2007 at 03:07:23PM +1300, Dr Bruce Griffiths wrote:

I am curious enough to try to figure this out for the PRR-10.   

It did occur to me that to use the 1 PPS to sample the accumulated phase
register you'd pretty obviously want to do this at well over 100 MHz in
order to get enough resolution (eg lack of quantizing noise) to usefully
track in the 10^12 area (100 MHz is only 10 ns time resolution, after
all).

This is obviously completely inconsistent with a 20 MHz clocked

system (50 ns per tick), though one with an internal PLL multiplier
might be good enough (easily done in a modern FPGA with these things
internal and 400 or better MHz clocks possible, but doubtful for a mid
90s design).

There is one obvious alternative - use the DDS to synthesize say

5 or 1 mhz and filter that with analog filtering (crystal filter) and
then use the 1 PPS from the Oncore to sample the 5 or 1 mhz with a fast
sampler (eg your suggestion of a TDC) at the time of the 1 PPS edge.
This provides whatever resolution the  analog A/D and sampler will do
without all the ramp generator complexity.  And does not involve any
form of synchronizer with its inherent uncertainty window.  (And of
course you then do synchronize the 1 PPS and read the coarse phase bits
from the phase accumulator sampled on the 1 PPS).

--
Dave Emery N1PRE,  die@dieconsulting.com  DIE Consulting, Weston, Mass 02493
"An empty zombie mind with a forlorn barely readable weatherbeaten
'For Rent' sign still vainly flapping outside on the weed encrusted pole - in
celebration of what could have been, but wasn't and is not to be now either."

David I. Emery wrote:

David

Modern TDC chips just use internal gate delays and either a delay locked
loop or periodic calibration to achieve subnanosecond resolution without
needing any external ramp generators etc.

Having the DDS and GPS receiver use the same clock eliminates the need
for any external ADC or TDC.
The GPS receiver can then use the DDS or an equivalent digital micro
phasestepper in conjunction with an analog bandpass filter to produce a
disciplined output frequency.

Alternatively the DDS or phase stepper can generate the GPS receiver
clock from the local frequency standard.
The GPS can then discipline its clock via the DDS or phase stepper using
GPS carrier and code phase measurements.
Of course, one would then have to write ones own GPS receiver firmware
to accomplish this.

Bruce