My understanding is that that is how the PRR-10s DO 

I would know this much more precisely if more detailed 

I do admit that without schematics or reverse 

And the other approach is to clock the DDS NCO chip 

Bruce, good to have you in the background with a look for the finer details. > A frequency multiplier, either within the DDS, or external to it is > required to generate a suitable DDS clock from either a 10MHz > or 20MHz input. Of course! That's why i use a AD9852 which features BOTH an internal programable frequency multiplier as well as 48 bit phase accumulator resolution. AFAIK you cannot get a dds chip with higher resolution at the time. The people who need higher resolutions use tricky design around the dds. Stanford Research for example uses a 48 Bit resolution in their CG635 clock generator but time multiplex the lsd of the dds input with a 16 bit resolution pwm signal to get a 64 bit resolution clock (at least when taking the mean over a longer time). Best regards Ulrich Bangert, DF6JB > -----Ursprüngliche Nachricht----- > Von: time-nuts-bounces@febo.com > [mailto:time-nuts-bounces@febo.com] Im Auftrag von Dr Bruce Griffiths > Gesendet: Samstag, 27. Januar 2007 23:43 > An: Discussion of precise time and frequency measurement > Betreff: Re: [time-nuts] Austron PRR-10 GPS discliplined Rb... > > > David > > David I. Emery wrote: > > On Sat, Jan 27, 2007 at 01:32:40PM +0100, Ulrich Bangert wrote: > > > >> Rob, > >> > >> are you absolutely sure it works this way? I experimented > a lot with > >> a 48 bit dds chip from analog devices for a GPSDO just to > learn that > >> THIS way worked not good. What however works good is to > imagine the > >> combination of OCXO and dds as kind of 'pure digital efc'. > That is: > >> The output of the DDS (and not the RB's) is divided doen > to a 1 pps > >> which is phase compared to the gps receiver. This makes > the system an > >> overall PLL closed loop as seen with conventional efc circuits, > >> however without the need for precise analogue circuitry, > which is why > >> i use it! > >> > >> > > > > My understanding is that that is how the PRR-10s DO > work. A DDS is > > used to synthesize 20 MHz from the input reference 10 MHz > and a 20 MHz > > VCXO is locked to this DDS output and divided down to produce 1 PPS > > to compare with the UT+ or M12M 1 PPS. And the phase > error data from > > that comparison is used to steer the DDS. So yes, the 20 > MHz is PLL > > locked to the GPS by twiddling the DDS. > > > > I would know this much more precisely if more detailed > documentation > > on this now obsolete product became available (hint hint), > but since I > > have several of the GPS locking boards now it may well > become worth > > it to get out the DMM on beep mode and start tracing etch - > and/or get > > out scope and logic analyzer and see what is going on... > > > > I do admit that without schematics or reverse > engineering there are > > some details that are a bit fuzzy - specifically what the relative > > clock domains are for the two clocks (20 MHz from the VCXO > and the 10 > > MHz from the Rb). I suppose one can handle this two ways - > use a DDS > > clocked with the 20 MHz VCXO to generate a 10 MHz signal and phase > > compare (at 10 MHz) this with the input 10 MHz to steer the > VCXO to lock > > with the Rb 10 MHz input as adjusted by the DDS NCO. This > implies that > > virtually all of the logic in the board is clocked at 20 MHz by the > > VCXO output, and that another channel of the primary NCO chip or a > > second one can be used to generate 1 PPS slewable in phase > to acquire initial lock > > with the GPS 1 PPS. In this configuration errors in the 1 > PPS phase > > would be use to adjust the DDS ratio so as to make it > synthesize the OFF > > frequency Rb reference input 10 MHz. > > > > And the other approach is to clock the DDS NCO chip > with the 10 MHz > > Rb reference input and use it to generate a corrected 20 MHz which > > can be used to phase lock the 20 MHz VCXO. This implies a > second 10 > > MHz clock domain for the DDS chip and related logic from > the 20 MHz VCXO > > world. The first approach strikes me as cleaner, frankly, as the > > board would have one clock rather than two... and if the > input clock > > disappeared (very possible in this application) there would > still be > > clock for everything if only as good as the VCXO and not reference > > quality. > > > > > > > The DDS will need to have an internal clock of at least 30MHz > or so to > generate a usable 10MHz output. > A frequency multiplier, either within the DDS, or external to it is > required to generate a suitable DDS clock from either a 10MHz > or 20MHz > input. > Although theoretically it is possible to generate 10MHz from a DDS > clocked at 20MHz, in practice the necessary brick wall analog > reconstruction filter is unrealisable. > > Bruce > > _______________________________________________ > time-nuts mailing list > time-nuts@febo.com > https://www.febo.com/cgi-> bin/mailman/listinfo/time-nuts >

Ulrich Bangert wrote: > Bruce, > > good to have you in the background with a look for the finer details. > > >> A frequency multiplier, either within the DDS, or external to it is >> required to generate a suitable DDS clock from either a 10MHz >> or 20MHz input. >> > > Of course! That's why i use a AD9852 which features BOTH an internal > programable frequency multiplier as well as 48 bit phase accumulator > resolution. AFAIK you cannot get a dds chip with higher resolution at > the time. The people who need higher resolutions use tricky design > around the dds. Stanford Research for example uses a 48 Bit resolution > in their CG635 clock generator but time multiplex the lsd of the dds > input with a 16 bit resolution pwm signal to get a 64 bit resolution > clock (at least when taking the mean over a longer time). > > Best regards > Ulrich Bangert, DF6JB > > >> -----Ursprüngliche Nachricht----- >> Von: time-nuts-bounces@febo.com >> [mailto:time-nuts-bounces@febo.com] Im Auftrag von Dr Bruce Griffiths >> Gesendet: Samstag, 27. Januar 2007 23:43 >> An: Discussion of precise time and frequency measurement >> Betreff: Re: [time-nuts] Austron PRR-10 GPS discliplined Rb... >> >> >> Ulrich Since an adjustment range of a few ppm suffices to correct the frequency error of an OCXO (even one that has aged for several decades) a cascaded mix and divide technique can be used to increase the resolution by another 16 bits or so whilst reducing the close in phase noise, reducing the phase noise floor, and reducing DDS output spur levels. The tradeoff is that the mix and divide technique increases the circuit complexity and cost somewhat, in that a mixer, a divider, a bandpass filter and an amplifier are required for each stage. It would also be possible to use a DDS plus a cascaded set of mix and divide modules to generate the reference frequency input for another set of cascaded mix and divide modules plus another DDS. The second circuit can then employ a longer chain of cascaded mix and divide modules to further extend the resolution by perhaps another 32 bits or more whilst retaining an adjustment range of say 10 -100 ppm. In practice there may be few applications for such a 96 bit resolution DDS with a 10-100ppm adjustment range. Bruce

Those of you who use multifrequency GPS antennas such as choke ring antennas may find the following article of some interest. The new Trimble antenna has better performance than a choke ring antenna especially if more than 2 frequencies are required. http://www.seilerinst.com/images/gps/products/gps5700/5700WPZephyrE.pdf Bruce

From: "Ulrich Bangert" <df6jb@ulrich-bangert.de> Subject: Re: [time-nuts] Austron PRR-10 GPS discliplined Rb... Date: Sat, 27 Jan 2007 13:24:48 +0100 Message-ID: <000a01c7420e$23c5cf10$03b2fea9@athlon> > Hi Magnus, Hi Ulrich, Sorry for the delay, but I made a little trip and just came back. > can you supply this manual??? No need. Just go to Symmetricoms manual archive. This was my way of flagging that it is there. Cheers, Magnus