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problem building E310 RFnoc

JM
Jason Matusiak
Fri, Jun 5, 2015 12:07 PM

This is my first foray into USRPs and I am trying to build the RFNOC for an E310. I have Vivado installed and have a webPACK license setup.

I went through the steps from the RFNoC:-Getting-Started on github and have my code all downloaded. I then go to the uhd/fpga-src/usrp3/top/e300 directory and run 'source setupenv.sh' and 'make cleanall' and 'make E310-RFNOC', but it errors out.

There are errors throughout the process, but the last one looks like:

2 Infos, 16 Warnings, 0 Critical Warnings and 1 Errors encountered.

synth_design failed

ERROR: [Runs 36-335] '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.dcp' is not a valid design checkpoint

INFO: [Common 17-206] Exiting Vivado at Fri Jun 5 05:03:49 2015...

make[1]: *** [bin] Error 1

make[1]: Leaving directory `/home/blah/uhd/fpga-src/usrp3/top/e300'

make: *** [E310_RFNOC] Error 2

I attached the build.log in case that might be helpful.

~Jason

JP
Jonathon Pendlum
Fri, Jun 5, 2015 4:51 PM

Hi Jason,

Do you have Vivado 2014.4 installed? This error typically occurs when
using a newer version such as 2015.1.

Jonathon

On Fri, Jun 5, 2015 at 5:07 AM, Jason Matusiak via USRP-users
usrp-users@lists.ettus.com wrote:

This is my first foray into USRPs and I am trying to build the RFNOC for an
E310.  I have Vivado installed and have a webPACK license setup.

I went through the steps from the RFNoC:-Getting-Started on github and have
my code all downloaded.  I then go to the uhd/fpga-src/usrp3/top/e300
directory and run 'source setupenv.sh' and 'make cleanall' and 'make
E310-RFNOC', but it errors out.

There are errors throughout the process, but the last one looks like:
2 Infos, 16 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Runs 36-335]
'/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.dcp'
is not a valid design checkpoint
INFO: [Common 17-206] Exiting Vivado at Fri Jun  5 05:03:49 2015...
make[1]: *** [bin] Error 1
make[1]: Leaving directory `/home/blah/uhd/fpga-src/usrp3/top/e300'
make: *** [E310_RFNOC] Error 2

I attached the build.log in case that might be helpful.

~Jason


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Hi Jason, Do you have Vivado 2014.4 installed? This error typically occurs when using a newer version such as 2015.1. Jonathon On Fri, Jun 5, 2015 at 5:07 AM, Jason Matusiak via USRP-users <usrp-users@lists.ettus.com> wrote: > This is my first foray into USRPs and I am trying to build the RFNOC for an > E310. I have Vivado installed and have a webPACK license setup. > > I went through the steps from the RFNoC:-Getting-Started on github and have > my code all downloaded. I then go to the uhd/fpga-src/usrp3/top/e300 > directory and run 'source setupenv.sh' and 'make cleanall' and 'make > E310-RFNOC', but it errors out. > > There are errors throughout the process, but the last one looks like: > 2 Infos, 16 Warnings, 0 Critical Warnings and 1 Errors encountered. > synth_design failed > ERROR: [Runs 36-335] > '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.dcp' > is not a valid design checkpoint > INFO: [Common 17-206] Exiting Vivado at Fri Jun 5 05:03:49 2015... > make[1]: *** [bin] Error 1 > make[1]: Leaving directory `/home/blah/uhd/fpga-src/usrp3/top/e300' > make: *** [E310_RFNOC] Error 2 > > I attached the build.log in case that might be helpful. > > ~Jason > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >