#-----------------------------------------------------------
# Vivado v2015.1 (64-bit)
# SW Build 1215546 on Mon Apr 27 19:07:21 MDT 2015
# IP Build 1209967 on Tue Apr 21 11:39:20 MDT 2015
# Start of session at: Fri Jun  5 05:03:24 2015
# Process ID: 4828
# Log file: /home/blah/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC/build.log
# Journal file: /home/blah/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC/e300.jou
#-----------------------------------------------------------
source /home/blah/uhd/fpga-src/usrp3/top/e300/build_e300.tcl
# source $::env(VIV_TOOLS_DIR)/scripts/viv_utils.tcl
## namespace eval ::vivado_utils {
##     # Export commands
##     namespace export \
##         initialize_project \
##         synthesize_design \
##         generate_post_synth_reports \
##         generate_post_place_reports \
##         generate_post_route_reports \
##         write_implementation_outputs \
##         get_top_module \
##         get_part_name \
##         get_vivado_mode
## 
##     # Required environment variables
##     variable g_top_module   $::env(VIV_TOP_MODULE)
##     variable g_part_name    $::env(VIV_PART_NAME)
##     variable g_output_dir   $::env(VIV_OUTPUT_DIR)
##     variable g_source_files $::env(VIV_SOURCE_FILES)
##     variable g_vivado_mode  $::env(VIV_MODE)
## 
##     # Optional environment variables
##     variable g_verilog_defs ""
##     if { [info exists ::env(VIV_VERILOG_DEFS) ] } {
##         set g_verilog_defs  $::env(VIV_VERILOG_DEFS)
##     }
##     variable g_include_dirs ""
##     if { [info exists ::env(VIV_INCLUDE_DIRS) ] } {
##         set g_include_dirs  $::env(VIV_INCLUDE_DIRS)
##     }
## }
## proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
##     variable g_top_module
##     variable g_part_name
##     variable g_output_dir
##     variable g_source_files
## 
##     file delete -force $g_output_dir/build.rpt
## 
##     if {$save_to_disk == 1} {
##         puts "BUILDER: Creating Vivado project ${g_top_module}_project.xpr for part $g_part_name"
##         create_project -part $g_part_name ${g_top_module}_project
##     } else {
##         puts "BUILDER: Creating Vivado project in memory for part $g_part_name"
##         create_project -in_memory -part $g_part_name
##     }
## 
##     foreach src_file $g_source_files {
##         set src_ext [file extension $src_file ]
##         if [expr [lsearch {.vhd .vhdl} $src_ext] >= 0] {
##             puts "BUILDER: Adding VHDL    : $src_file"
##             read_vhdl -library work $src_file
##         } elseif [expr [lsearch {.v} $src_ext] >= 0] {
##             puts "BUILDER: Adding Verilog : $src_file"
##             read_verilog $src_file
##         } elseif [expr [lsearch {.xdc} $src_ext] >= 0] {
##             puts "BUILDER: Adding XDC     : $src_file"
##             read_xdc $src_file
##         } elseif [expr [lsearch {.xci} $src_ext] >= 0] {
##             puts "BUILDER: Adding IP      : $src_file"
##             read_ip $src_file
##         } elseif [expr [lsearch {.ngc .edif} $src_ext] >= 0] {
##             puts "BUILDER: Adding Netlist : $src_file"
##             read_edif $src_file
##         } else {
##             puts "BUILDER: \[WARNING\] File ignored!!!: $src_file"
##         }
##     }
## 
##     puts "BUILDER: Refreshing IP"
##     generate_target all [get_ips *]
##     synth_ip [get_ips *]
## 
##     puts "BUILDER: Setting $g_top_module as the top module"
##     set_property top $g_top_module [current_fileset]
## }
## proc ::vivado_utils::synthesize_design {args} {
##     variable g_top_module
##     variable g_part_name
##     variable g_verilog_defs
##     variable g_include_dirs
## 
##     set vdef_args ""
##     foreach vdef $g_verilog_defs {
##         set vdef_args [concat $vdef_args "-verilog_define $vdef"]
##     }
##     set incdir_args ""
##     if { [string compare $g_include_dirs ""] != 0 } {
##         set incdir_args "-include_dirs $g_include_dirs"
##     }
## 
##     set synth_cmd "synth_design -top $g_top_module -part $g_part_name"
##     set synth_cmd [concat $synth_cmd $vdef_args]
##     set synth_cmd [concat $synth_cmd $incdir_args]
##     set synth_cmd [concat $synth_cmd $args]
##     puts "BUILDER: Synthesizing design"
##     eval $synth_cmd
## }
## proc ::vivado_utils::generate_post_synth_reports {} {
##     variable g_output_dir
## 
##     puts "BUILDER: Writing post-synthesis checkpoint"
##     write_checkpoint -force $g_output_dir/post_synth 
##     puts "BUILDER: Writing post-synthesis reports"
##     report_utilization -file $g_output_dir/post_synth_util.rpt 
##     report_drc -ruledeck methodology_checks -file $g_output_dir/methodology.rpt 
##     report_high_fanout_nets -file $g_output_dir/high_fanout_nets.rpt 
## }
## proc ::vivado_utils::generate_post_place_reports {} {
##     variable g_output_dir
## 
##     puts "BUILDER: Writing post-placement checkpoint"
##     write_checkpoint -force $g_output_dir/post_place 
##     puts "BUILDER: Writing post-placement reports"
##     report_clock_utilization -file $g_output_dir/clock_util.rpt 
##     report_utilization -file $g_output_dir/post_place_util.rpt 
##     report_timing -sort_by group -max_paths 5 -path_type summary -file $g_output_dir/post_place_timing.rpt 
## }
## proc ::vivado_utils::generate_post_route_reports {} {
##     variable g_output_dir
## 
##     puts "BUILDER: Writing post-route checkpoint"
##     write_checkpoint -force $g_output_dir/post_route 
##     puts "BUILDER: Writing post-route reports"
##     report_timing_summary -file $g_output_dir/post_route_timing_summary.rpt 
##     report_utilization -file $g_output_dir/post_route_util.rpt 
##     report_power -file $g_output_dir/post_route_power.rpt 
##     report_drc -file $g_output_dir/post_imp_drc.rpt 
##     report_timing -sort_by group -max_paths 10 -path_type summary -file $g_output_dir/post_route_timing.rpt 
## }
## proc ::vivado_utils::write_implementation_outputs {} {
##     variable g_output_dir
##     variable g_top_module
## 
##     puts "BUILDER: Writing implementation netlist and XDC"
##     write_verilog -force $g_output_dir/${g_top_module}_impl_netlist.v 
##     write_xdc -no_fixed_only -force $g_output_dir/${g_top_module}_impl.xdc 
##     puts "BUILDER: Writing bitstream"
##     write_bitstream -force -bin_file $g_output_dir/${g_top_module}.bit 
##     puts "BUILDER: Writing debug probes"
##     write_debug_probes -force $g_output_dir/${g_top_module}.ltx
##     puts "BUILDER: Writing export report"
##     report_utilization -omit_locs -file $g_output_dir/build.rpt
##     report_timing_summary -no_detailed_paths -warn_on_violation -file $g_output_dir/build.rpt -append
## }
## proc ::vivado_utils::close_batch_project {} {
##     variable g_vivado_mode
##     
##     if [string equal $g_vivado_mode "batch"] {
##         puts "BUILDER: Closing project"
##         close_project
##     } else {
##         puts "BUILDER: In GUI mode. Leaving project open."
##     }
## }
## proc ::vivado_utils::get_top_module {} {
##     variable g_top_module
##     return $g_top_module
## }
## proc ::vivado_utils::get_part_name {} {
##     variable g_part_name
##     return $g_part_name
## }
## proc ::vivado_utils::get_vivado_mode {} {
##     variable g_vivado_mode
##     return $g_vivado_mode
## }
# vivado_utils::initialize_project
BUILDER: Creating Vivado project in memory for part xc7z020clg484-1
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/e300_ps.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/e300_core.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/ppsloop.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/ad5662_auto_spi.v
BUILDER: Adding XDC     : /home/blah/uhd/fpga-src/usrp3/top/e300/e300.xdc
BUILDER: Adding XDC     : /home/blah/uhd/fpga-src/usrp3/top/e300/timing.xdc
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/e300.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/zynq_fifo/zf_arbiter.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/zynq_fifo/zf_stream_to_host.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/zynq_fifo/zf_host_to_stream.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/zynq_fifo/zf_slave_readback.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/zynq_fifo/zf_slave_settings.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/zynq_fifo/zynq_fifo_top.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_mux4.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_mux8.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_demux4.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_demux8.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_mux.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_demux.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_fifo_short.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_fifo_flop.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_fifo_flop2.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_fifo_bram.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_packet_gate.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_fifo.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_fifo_cascade.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_fifo64_to_fifo32.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_fifo32_to_fifo64.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_fifo_2clk.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_fifo_2clk_cascade.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_loopback.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/fifo/axi_filter_mux4.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/new_tx_control.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/new_tx_deframer.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/tx_responder.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/trigger_context_pkt.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/context_packet_gen.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/new_rx_control.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/new_rx_framer.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/chdr_16sc_to_xxxx_chain.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/chdr_xxxx_to_16sc_chain.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/chdr_16sc_to_12sc.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/chdr_12sc_to_16sc.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/chdr_16sc_to_8sc.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/chdr_8sc_to_16sc.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/chdr_16sc_to_32f.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/chdr_32f_to_16sc.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/chdr_32f_to_16s.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/xxf_to_xxs.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/chdr_16s_to_32f.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/xxs_to_xxf.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/float_to_iq.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/vita/iq_to_float.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/timing/time_compare.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/timing/timekeeper.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/timing/pps.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/ddc_chain_x300.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/ddc_chain.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/duc_chain.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/sign_extend.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/cordic_z24.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/clip_reg.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/cordic_stage.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/clip.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/cic_strober.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/cic_decim.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/cic_interp.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/cic_dec_shifter.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/cic_int_shifter.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/small_hb_dec.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/small_hb_int.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/hb_dec.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/hb_interp.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/add_then_mac.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/hb47_int.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/round_sd.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/add2_and_clip_reg.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/add2_and_clip.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/add2.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/add2_reg.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/add2_and_round_reg.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/add2_and_round.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/round_reg.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/round.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/srl.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/acc.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/rx_frontend.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/tx_frontend.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/dsp/rx_dcoffset.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/eth_dispatch.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/ip_hdr_checksum.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/vrlp_eth_framer.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/chdr_eth_framer.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/eth_interface.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/vrlp_to_compressed_vita.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/compressed_vita_to_vrlp.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/source_flow_control.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/cvita_insert_tlast.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/cvita_dest_lookup.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/cvita_chunker.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/cvita_dechunker.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/axis_packet_debug.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/cvita_packet_debug.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/packet_proc/fix_short_packet.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/reset_sync.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/por_gen.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/gpio_atr.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/simple_spi_core.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/simple_i2c_core.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/setting_reg.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/axi_setting_reg.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/settings_bus_crossclock.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/radio_ctrl_proc.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/ram_2port.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/axi_crossbar.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/axi_slave_mux.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/axi_fifo_header.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/arb_qualify_master.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/axi_forwarding_cam.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/axi_test_vfifo.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/dram_2port.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/cvita_uart.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/serial_to_settings.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/filter_bad_sid.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/synchronizer.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/binary_encoder.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/priority_encoder.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/control/priority_encoder_one_hot.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/radio/radio.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/io_cap_gen/catcap_ddr_cmos.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/io_cap_gen/catgen_ddr_cmos.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/io_cap_gen/catcodec_ddr_cmos.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbdec1.v
BUILDER: Adding Netlist : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbdec1.ngc
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbdec2.v
BUILDER: Adding Netlist : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbdec2.ngc
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbdec3.v
BUILDER: Adding Netlist : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbdec3.ngc
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbint1.v
BUILDER: Adding Netlist : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbint1.ngc
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbint2.v
BUILDER: Adding Netlist : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbint2.ngc
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbint3.v
BUILDER: Adding Netlist : /home/blah/uhd/fpga-src/usrp3/top/e300/coregen_dsp/hbint3.ngc
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'axi3_to_axi4lite_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi3_to_axi4lite_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi3_to_axi4lite_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi3_to_axi4lite_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi3_to_axi4lite_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_fifo_512x64/axi4_fifo_512x64.xci
WARNING: [IP_Flow 19-3664] IP 'axi4_fifo_512x64' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_fifo_512x64/axi4_fifo_512x64.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi4_fifo_512x64' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_fifo_512x64/axi4_fifo_512x64_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi4_fifo_512x64' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_fifo_512x64/axi4_fifo_512x64_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi4_fifo_512x64' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_fifo_512x64/axi4_fifo_512x64_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi4_fifo_512x64' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_fifo_512x64/axi4_fifo_512x64_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.xci
WARNING: [IP_Flow 19-3664] IP 'axi4_to_axi3_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi4_to_axi3_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi4_to_axi3_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi4_to_axi3_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi4_to_axi3_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover.xci
WARNING: [IP_Flow 19-3664] IP 'axi_datamover' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_datamover' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_datamover' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_datamover' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_datamover' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm.xci
WARNING: [IP_Flow 19-3664] IP 'catcodec_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'catcodec_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'catcodec_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'catcodec_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'catcodec_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.xci
WARNING: [IP_Flow 19-3664] IP 'e300_ps_fclk0_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'e300_ps_fclk0_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'e300_ps_fclk0_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'e300_ps_fclk0_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'e300_ps_fclk0_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7.xci
WARNING: [IP_Flow 19-3664] IP 'processing_system7' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'processing_system7' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'processing_system7' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'processing_system7' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'processing_system7' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.xci
WARNING: [IP_Flow 19-3664] IP 'fifo_4k_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'fifo_4k_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'fifo_4k_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'fifo_4k_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'fifo_4k_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.xci
WARNING: [IP_Flow 19-3664] IP 'fifo_short_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'fifo_short_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'fifo_short_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'fifo_short_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'fifo_short_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk_funcsim.v'. Please regenerate to continue.
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/chdr_framer.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/chdr_deframer.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_shell.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/simple_axi_wrapper.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/axi_wrapper.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/axi_bit_reduce.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_axi_fifo_loopback.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fir_filter.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_fft.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_null_source_sink.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_schmidl_cox.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_packet_resizer.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_split_stream.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_vector_iir.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_addsub.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_window.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_keep_one_in_n.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_block_pfb.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/pfb.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/pfb_stage.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/null_source.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/schmidl_cox.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/split_stream.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/split_stream_fifo.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/conj.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/delay.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/delay_type2.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/delay_type3.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/complex_to_magsq.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/phase_acc.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/periodic_framer.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/threshold_scaled.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/moving_sum.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/peak_finder.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/window.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/counter.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/ram_to_fifo.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/const.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/const_sreg.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/cmul.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/cadd.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_input_port.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/noc_output_port.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/keep_one_in_n_vec.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/vector_iir.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/addsub.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/packet_resizer.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/axi_pipe.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/mult.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/mult_add.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/mult_rc.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/mult_add_rc.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/fft_shift.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/axi_pipe_join.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/axi_pipe_mac.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/axi_round_and_clip_complex.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/axi_join.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/split_complex.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/axi_round_and_clip.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/join_complex.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/axi_round.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/axi_clip.v
BUILDER: Adding Verilog : /home/blah/uhd/fpga-src/usrp3/lib/rfnoc/complex_to_mag_approx.v
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fir/axi_fir.xci
WARNING: [IP_Flow 19-3664] IP 'axi_fir' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fir/axi_fir_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_fir' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fir/axi_fir.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_fir' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fir/axi_fir_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_fir' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fir/axi_fir_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_fir' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fir/axi_fir_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fft/axi_fft.xci
WARNING: [IP_Flow 19-3664] IP 'axi_fft' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fft/axi_fft_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_fft' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fft/axi_fft.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_fft' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fft/axi_fft_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_fft' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fft/axi_fft_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'axi_fft' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fft/axi_fft_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_to_magphase/complex_to_magphase.xci
WARNING: [IP_Flow 19-3664] IP 'complex_to_magphase' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_to_magphase/complex_to_magphase_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'complex_to_magphase' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_to_magphase/complex_to_magphase.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'complex_to_magphase' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_to_magphase/complex_to_magphase_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'complex_to_magphase' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_to_magphase/complex_to_magphase_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'complex_to_magphase' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_to_magphase/complex_to_magphase_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_multiplier/complex_multiplier.xci
WARNING: [IP_Flow 19-3664] IP 'complex_multiplier' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_multiplier/complex_multiplier_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'complex_multiplier' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_multiplier/complex_multiplier.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'complex_multiplier' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_multiplier/complex_multiplier_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'complex_multiplier' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_multiplier/complex_multiplier_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'complex_multiplier' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_multiplier/complex_multiplier_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/cordic_rotator/cordic_rotator.xci
WARNING: [IP_Flow 19-3664] IP 'cordic_rotator' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/cordic_rotator/cordic_rotator_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'cordic_rotator' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/cordic_rotator/cordic_rotator.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'cordic_rotator' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/cordic_rotator/cordic_rotator_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'cordic_rotator' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/cordic_rotator/cordic_rotator_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'cordic_rotator' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/cordic_rotator/cordic_rotator_funcsim.v'. Please regenerate to continue.
BUILDER: Adding IP      : /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int32/divide_int32.xci
WARNING: [IP_Flow 19-3664] IP 'divide_int32' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int32/divide_int32_funcsim.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'divide_int32' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int32/divide_int32.dcp'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'divide_int32' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int32/divide_int32_stub.v'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'divide_int32' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int32/divide_int32_stub.vhdl'. Please regenerate to continue.
WARNING: [IP_Flow 19-3664] IP 'divide_int32' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int32/divide_int32_funcsim.v'. Please regenerate to continue.
BUILDER: Refreshing IP
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.xci
Locked reason: 
* IP definition 'AXI Protocol Converter (2.1)' for IP 'axi3_to_axi4lite_protocol_converter' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_fifo_512x64/axi4_fifo_512x64.xci
Locked reason: 
* IP definition 'AXI Data FIFO (2.1)' for IP 'axi4_fifo_512x64' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter.xci
Locked reason: 
* IP definition 'AXI Protocol Converter (2.1)' for IP 'axi4_to_axi3_protocol_converter' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover.xci
Locked reason: 
* IP definition 'AXI DataMover (5.1)' for IP 'axi_datamover' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fft/axi_fft.xci
Locked reason: 
* IP definition 'Fast Fourier Transform (9.0)' for IP 'axi_fft' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fir/axi_fir.xci
Locked reason: 
* IP definition 'FIR Compiler (7.2)' for IP 'axi_fir' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm.xci
Locked reason: 
* IP definition 'Clocking Wizard (5.1)' for IP 'catcodec_mmcm' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_multiplier/complex_multiplier.xci
Locked reason: 
* IP definition 'Complex Multiplier (6.0)' for IP 'complex_multiplier' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_to_magphase/complex_to_magphase.xci
Locked reason: 
* IP definition 'CORDIC (6.0)' for IP 'complex_to_magphase' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/cordic_rotator/cordic_rotator.xci
Locked reason: 
* IP definition 'CORDIC (6.0)' for IP 'cordic_rotator' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int32/divide_int32.xci
Locked reason: 
* IP definition 'Divider Generator (5.1)' for IP 'divide_int32' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.xci
Locked reason: 
* IP definition 'Clocking Wizard (5.1)' for IP 'e300_ps_fclk0_mmcm' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk.xci
Locked reason: 
* IP definition 'FIFO Generator (12.0)' for IP 'fifo_4k_2clk' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk.xci
Locked reason: 
* IP definition 'FIFO Generator (12.0)' for IP 'fifo_short_2clk' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7.xci
Locked reason: 
* IP definition 'ZYNQ7 Processing System (5.5)' for IP 'processing_system7' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'axi3_to_axi4lite_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top axi3_to_axi4lite_protocol_converter -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'axi3_to_axi4lite_protocol_converter' is locked:
* IP definition 'AXI Protocol Converter (2.1)' for IP 'axi3_to_axi4lite_protocol_converter' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
****** Webtalk v2015.1 (64-bit)
  **** SW Build 1215546 on Mon Apr 27 19:07:21 MDT 2015
  **** IP Build 1209967 on Tue Apr 21 11:39:20 MDT 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source /home/blah/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC/.Xil/Vivado-4828-ubuntu/webtalk/labtool_webtalk.tcl -notrace
INFO: [Common 17-186] '/home/blah/uhd/fpga-src/usrp3/top/e300/build-E310_RFNOC/.Xil/Vivado-4828-ubuntu/webtalk/usage_statistics_ext_labtool.xml' has been successfully sent to Xilinx on Fri Jun  5 05:03:40 2015. For additional details about this file, please refer to the WebTalk help file at /opt/Xilinx/Vivado/2015.1/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Fri Jun  5 05:03:40 2015...
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'axi4_fifo_512x64' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_fifo_512x64/axi4_fifo_512x64_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top axi4_fifo_512x64 -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'axi4_fifo_512x64' is locked:
* IP definition 'AXI Data FIFO (2.1)' for IP 'axi4_fifo_512x64' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'axi4_to_axi3_protocol_converter' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi4_to_axi3_protocol_converter/axi4_to_axi3_protocol_converter_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top axi4_to_axi3_protocol_converter -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'axi4_to_axi3_protocol_converter' is locked:
* IP definition 'AXI Protocol Converter (2.1)' for IP 'axi4_to_axi3_protocol_converter' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'axi_datamover' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_datamover/axi_datamover_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top axi_datamover -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'axi_datamover' is locked:
* IP definition 'AXI DataMover (5.1)' for IP 'axi_datamover' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'axi_fft' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fft/axi_fft_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top axi_fft -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'axi_fft' is locked:
* IP definition 'Fast Fourier Transform (9.0)' for IP 'axi_fft' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'axi_fir' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi_fir/axi_fir_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top axi_fir -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'axi_fir' is locked:
* IP definition 'FIR Compiler (7.2)' for IP 'axi_fir' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'catcodec_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top catcodec_mmcm -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm.xci

WARNING: [IP_Flow 19-2162] IP 'catcodec_mmcm' is locked:
* IP definition 'Clocking Wizard (5.1)' for IP 'catcodec_mmcm' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 3 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'complex_multiplier' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_multiplier/complex_multiplier_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top complex_multiplier -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'complex_multiplier' is locked:
* IP definition 'Complex Multiplier (6.0)' for IP 'complex_multiplier' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'complex_to_magphase' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/complex_to_magphase/complex_to_magphase_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top complex_to_magphase -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'complex_to_magphase' is locked:
* IP definition 'CORDIC (6.0)' for IP 'complex_to_magphase' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'cordic_rotator' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/cordic_rotator/cordic_rotator_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top cordic_rotator -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'cordic_rotator' is locked:
* IP definition 'CORDIC (6.0)' for IP 'cordic_rotator' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'divide_int32' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/divide_int32/divide_int32_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top divide_int32 -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'divide_int32' is locked:
* IP definition 'Divider Generator (5.1)' for IP 'divide_int32' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'e300_ps_fclk0_mmcm' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top e300_ps_fclk0_mmcm -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.xci

WARNING: [IP_Flow 19-2162] IP 'e300_ps_fclk0_mmcm' is locked:
* IP definition 'Clocking Wizard (5.1)' for IP 'e300_ps_fclk0_mmcm' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 3 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'fifo_4k_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_4k_2clk/fifo_4k_2clk_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top fifo_4k_2clk -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'fifo_4k_2clk' is locked:
* IP definition 'FIFO Generator (12.0)' for IP 'fifo_4k_2clk' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'fifo_short_2clk' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/fifo_short_2clk/fifo_short_2clk_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top fifo_short_2clk -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'fifo_short_2clk' is locked:
* IP definition 'FIFO Generator (12.0)' for IP 'fifo_short_2clk' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.1/data/ip'.
WARNING: [IP_Flow 19-3664] IP 'processing_system7' generated file not found '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/processing_system7/processing_system7_funcsim.vhdl'. Please regenerate to continue.
Command: synth_design -top processing_system7 -part xc7z020clg484-1 -mode out_of_context
Starting synth_design
WARNING: [IP_Flow 19-2162] IP 'processing_system7' is locked:
* IP definition 'ZYNQ7 Processing System (5.5)' for IP 'processing_system7' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Vivado 12-398] No designs are open
INFO: [Vivado 12-3441] generate_netlist_ip - operation complete
synth_ip: Time (s): cpu = 00:00:09 ; elapsed = 00:00:12 . Memory (MB): peak = 990.195 ; gain = 73.270 ; free physical = 59 ; free virtual = 1282
BUILDER: Setting e300 as the top module
# vivado_utils::synthesize_design
BUILDER: Synthesizing design
Command: synth_design -top e300 -part xc7z020clg484-1 -verilog_define RFNOC=1 -verilog_define E310=1 -verilog_define GIT_HASH=F25bc7e8
Starting synth_design
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Implementation target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/catcodec_mmcm/catcodec_mmcm.xci
/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/e300_ps_fclk0_mmcm/e300_ps_fclk0_mmcm.xci

WARNING: [IP_Flow 19-2162] IP 'axi3_to_axi4lite_protocol_converter' is locked:
* IP definition 'AXI Protocol Converter (2.1)' for IP 'axi3_to_axi4lite_protocol_converter' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'axi4_fifo_512x64' is locked:
* IP definition 'AXI Data FIFO (2.1)' for IP 'axi4_fifo_512x64' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'axi4_to_axi3_protocol_converter' is locked:
* IP definition 'AXI Protocol Converter (2.1)' for IP 'axi4_to_axi3_protocol_converter' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'axi_datamover' is locked:
* IP definition 'AXI DataMover (5.1)' for IP 'axi_datamover' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'catcodec_mmcm' is locked:
* IP definition 'Clocking Wizard (5.1)' for IP 'catcodec_mmcm' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'e300_ps_fclk0_mmcm' is locked:
* IP definition 'Clocking Wizard (5.1)' for IP 'e300_ps_fclk0_mmcm' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'processing_system7' is locked:
* IP definition 'ZYNQ7 Processing System (5.5)' for IP 'processing_system7' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'fifo_4k_2clk' is locked:
* IP definition 'FIFO Generator (12.0)' for IP 'fifo_4k_2clk' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'fifo_short_2clk' is locked:
* IP definition 'FIFO Generator (12.0)' for IP 'fifo_short_2clk' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'axi_fir' is locked:
* IP definition 'FIR Compiler (7.2)' for IP 'axi_fir' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'axi_fft' is locked:
* IP definition 'Fast Fourier Transform (9.0)' for IP 'axi_fft' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'complex_to_magphase' is locked:
* IP definition 'CORDIC (6.0)' for IP 'complex_to_magphase' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'complex_multiplier' is locked:
* IP definition 'Complex Multiplier (6.0)' for IP 'complex_multiplier' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'cordic_rotator' is locked:
* IP definition 'CORDIC (6.0)' for IP 'cordic_rotator' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
WARNING: [IP_Flow 19-2162] IP 'divide_int32' is locked:
* IP definition 'Divider Generator (5.1)' for IP 'divide_int32' has a different revision in the IP Catalog.
Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information.
Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z020'
INFO: [Common 17-83] Releasing license: Synthesis
2 Infos, 16 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Runs 36-335] '/home/blah/uhd/fpga-src/usrp3/top/e300/build-ip/xc7z020clg484-1/axi3_to_axi4lite_protocol_converter/axi3_to_axi4lite_protocol_converter.dcp' is not a valid design checkpoint
INFO: [Common 17-206] Exiting Vivado at Fri Jun  5 05:03:49 2015...