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Discussion and technical support related to USRP, UHD, RFNoC
View all threadsBuilding x310 FPGA image for UHD 4.3.0
I’m trying to build the x310 base image on RHEL9. I keep getting build errors, despite the fact that I built UHD 4.2 no problem. The steps I followed:
-
Check out the v4.3.0.0 tag
-
source setupenv.sh --vivado-path=/path/to/Xilinx/Vivado/
-
make X310_XG
Did the process for building change? Has anybody else encountered problems?
Here is the error message I’m getting plus some context:
---=======================
BUILDER: Building IP axi_hb31
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31
BUILDER: Retargeting IP to part kintex7/xc7k410t/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log axi_hb31.log -nojournal
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci
[00:00:19] Current task: Initialization +++ Current Phase: Starting
[00:00:19] Current task: Initialization +++ Current Phase: Finished
[00:00:19] Executing Tcl: synth_design -top axi_hb31 -part xc7k410tffg900-2 -mode out_of_context
[00:00:19] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
[00:00:20] Current task: Synthesis +++ Current Phase: Starting
ERROR: [Vivado 12-398] No designs are open
[00:00:20] Current task: Synthesis +++ Current Phase: Finished
[00:00:20] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location: /afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31
make[1]: *** [/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc:20: LIB_IP_AXI_HB31_TRGT] Error 1
make[1]: Leaving directory '/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300'
make: *** [Makefile:80: X310_IP] Error 2
It says the IP is locked. Perhaps you have old IP left over from a previous
build that used an older Vivado version (the Vivado version changed with
UHD 4.3). Try doing "make cleanall" to remove all the IP before building it
again. Also, do a 'git status' and make sure you don't have any extra files
in the "ip" directories that need to be removed. Then try running 'make
X310_XG " again.
Wade
On Fri, Dec 23, 2022 at 10:52 AM ri28856@mit.edu wrote:
I’m trying to build the x310 base image on RHEL9. I keep getting build
errors, despite the fact that I built UHD 4.2 no problem. The steps I
followed:
1.
Check out the v4.3.0.0 tag
2.
source setupenv.sh --vivado-path=/path/to/Xilinx/Vivado/
3.
make X310_XG
Did the process for building change? Has anybody else encountered problems?
Here is the error message I’m getting plus some context:
---=======================
BUILDER: Building IP axi_hb31
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31
BUILDER: Retargeting IP to part kintex7/xc7k410t/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source
/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl
-log axi_hb31.log -nojournal
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the
following file is locked:
/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the
following file is locked:
/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci
[00:00:19] Current task: Initialization +++ Current Phase: Starting
[00:00:19] Current task: Initialization +++ Current Phase: Finished
[00:00:19] Executing Tcl: synth_design -top axi_hb31 -part
xc7k410tffg900-2 -mode out_of_context
[00:00:19] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products
for Synthesis target. These output products could be required for
synthesis, please generate the output products using the generate_target or
synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources
specified
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
[00:00:20] Current task: Synthesis +++ Current Phase: Starting
ERROR: [Vivado 12-398] No designs are open
[00:00:20] Current task: Synthesis +++ Current Phase: Finished
[00:00:20] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location:
/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31
make[1]: ***
[/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc:20:
LIB_IP_AXI_HB31_TRGT] Error 1
make[1]: Leaving directory
'/afs/mitll/usr/ri28856/public/uhd/fpga/usrp3/top/x300'
make: *** [Makefile:80: X310_IP] Error 2
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Here are my next steps:
-
git clone https://github.com/EttusResearch/uhd.git clean_uhd
-
git checkout v4.3.0.0
-
source setupenv.sh --vivado-path=/path/to/Xilinx/Vivado/
-
make cleanall
-
make X310_XG
I get a very similar error:
---=======================
BUILDER: Building IP axi_hb31
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location: /afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31
BUILDER: Retargeting IP to part kintex7/xc7k410t/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source /afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl -log axi_hb31.log -nojournal
[00:00:13] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci
[00:00:13] Current task: Initialization +++ Current Phase: Finished
[00:00:13] Executing Tcl: synth_design -top axi_hb31 -part xc7k410tffg900-2 -mode out_of_context
[00:00:13] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products for Synthesis target. These output products could be required for synthesis, please generate the output products using the generate_target or synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:14] Current task: Synthesis +++ Current Phase: Starting
[00:00:14] Current task: Synthesis +++ Current Phase: Finished
[00:00:14] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location: /afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31
make[1]: *** [/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc:20: LIB_IP_AXI_HB31_TRGT] Error 1
make[1]: Leaving directory '/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300'
You probably need to install Xilinx patch AR76780. See the dependencies
section in the manual for links to the patch:
https://files.ettus.com/manual/md_usrp3_build_instructions.html
UHD has already been updated to give you an error when this patch is not
installed and you try to build the FPGA, but that wasn't fixed until after
4.3 was released.
Wade
On Tue, Jan 3, 2023 at 2:40 PM ri28856@mit.edu wrote:
Here are my next steps:
1.
git clone https://github.com/EttusResearch/uhd.git clean_uhd
2.
git checkout v4.3.0.0
3.
source setupenv.sh --vivado-path=/path/to/Xilinx/Vivado/
4.
make cleanall
5.
make X310_XG
I get a very similar error:
---=======================
BUILDER: Building IP axi_hb31
---=======================
BUILDER: Staging IP in build directory...
BUILDER: Reserving IP location:
/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31
BUILDER: Retargeting IP to part kintex7/xc7k410t/ffg900/-2...
BUILDER: Building IP...
[00:00:00] Executing command: vivado -mode batch -source
/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/tools/scripts/viv_generate_ip.tcl
-log axi_hb31.log -nojournal
[00:00:13] Current task: Initialization +++ Current Phase: Starting
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the
following file is locked:
/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci
CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the
following file is locked:
/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xci
[00:00:13] Current task: Initialization +++ Current Phase: Finished
[00:00:13] Executing Tcl: synth_design -top axi_hb31 -part
xc7k410tffg900-2 -mode out_of_context
[00:00:13] Starting Synthesis Command
WARNING: [Vivado_Tcl 4-391] The following IPs are missing output products
for Synthesis target. These output products could be required for
synthesis, please generate the output products using the generate_target or
synth_ip command before running synth_design.
WARNING: [IP_Flow 19-2162] IP 'axi_hb31' is locked:
ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources
specified
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
ERROR: [Common 17-53] User Exception: No open design. Please open an
elaborated, synthesized or implemented design before executing this command.
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
CRITICAL WARNING: [IP_Flow 19-4739] Writing uncustomized BOM file
'/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/axi_hb31.xml'
ERROR: [Vivado 12-398] No designs are open
[00:00:14] Current task: Synthesis +++ Current Phase: Starting
[00:00:14] Current task: Synthesis +++ Current Phase: Finished
[00:00:14] Process terminated. Status: Failure
---=======================
Warnings: 3
Critical Warnings: 7
Errors: 8
BUILDER: Releasing IP location:
/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31
make[1]: ***
[/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/lib/ip/axi_hb31/Makefile.inc:20:
LIB_IP_AXI_HB31_TRGT] Error 1
make[1]: Leaving directory
'/afs/mitll/usr/ri28856/public/clean_uhd/fpga/usrp3/top/x300'
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I noticed that part of the manual but ignored it because it sounds like it only applies to the n3 and x4 family of USRPs, and I’m using an x310. Is that not the case?
Regardless I’ll work on installing the patch and try again.
Oh, thanks for pointing that out! Maybe that was correct at one point, but
the patch is definitely required for X310 as well in UHD 4.3. I'll see that
this gets changed in the manual.
Wade
On Tue, Jan 3, 2023 at 3:19 PM ri28856@mit.edu wrote:
I noticed that part of the manual but ignored it because it sounds like it
only applies to the n3 and x4 family of USRPs, and I’m using an x310. Is
that not the case?
Regardless I’ll work on installing the patch and try again.
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