5>10 doubler and old Toko RF catalogue (Cirkit 2nd ed. 1994)
Am 30.01.2015 um 02:41 schrieb Alexander Pummer:
And the narrow notch for the harmonic is not required anyway, since
the fundamental is fare enough, therefore a high Q LC trap will work
better, also with the setting of the biasing af the active devices the
spures could be reduced to [ just observe the output with a spectrum
analyzer and set the bias of one site to minimum harmonics, there will
be no common optimum for all harmonics, but a good compromise could be
achieved ]
As usual, it depends. If you want absolutely deep notches, it is easy
with the usual molded chokes
to produce craters at 5 and 15 MHz that meet at 10 MHz, even producing
some loss there.
The harmonics are gone, then.
At the -3dB point of a resonator we have 45° phase shift, now calculate
how many ps delay that
is at 10 MHz and then speculate on temperature stability.
On MY doubler board, Amidon toroids are in the layout, too, and I have
written that they are good enough.
They are hard to get. I have heard that Amidon is really Micrometals,
but have no cross
reference. A good alternative would be Siemens K1 pot cores, but they
are much too big and probably only NOS.
But everybody can get 5 and 15 MHz crystals for 35 cents.
BTW, this is the spectrum of a Morion MV89A that happenes to be on my table:
<
https://picasaweb.google.com/lh/photo/4UEjkc8uy_vkE5nTUR0BEdMTjNZETYmyPJy0liipFm0?feat=directlink
10 dB external attenuator. Could use some filtering, too.
regards, Gerhard
ps
My two BF862 are quite different. delta Vsource = 100mV.
Changing that would be the cheapest improvement.
On Fri, Jan 30, 2015 at 07:35:34PM +0100, Gerhard Hoffmann wrote:
As usual, it depends. If you want absolutely deep notches, it is
easy with the usual molded chokes
to produce craters at 5 and 15 MHz that meet at 10 MHz, even
producing some loss there.
Hello.
Let me sum up everything and please correct me:
the square-law characteristic of devices should be avoided, so the
configuration of the doubler must be some sort of "ideal" full wave rectifier
it's better to use diode-connected transistors like the 2N2222 because they are
less noisy than Schottky diodes at frequency < 40MHz (what about the normal
P-N diodes?)
matching is very important, so monolithic doubles or quadruples could be the
right choice, provided their other characteristics are compatible and the
substrate connection is not a problem
bandpass filtering must be avoided because of added unwanted
temperature-dependent phase shifts, so harmonic suppression should be obtained
by notch filtering
the notch filters could be made using quartz resonators but their high
impedance versus LC ones should be taken into account and, anyway, it's
difficult to find exactly tuned quartz (particularly for the higher harmonics
because of the overtone cut) - the sharpness of quartz filtering is not needed
anyway because the harmonics are distant enough for LC filters (what about
ceramic resonators?)
I add some questions.
I saw that most of the doublers out there are using a center tapped transformer
to obtain +-180 while the Racal circuit use a single ended input / balanced
output transistor discrete differential amplifier, thus combining phase
splitting with gain and impedance matching (but not isolation).
That configuration should be avoided because the transformer is normally a
better matched splitter?
On the base of many considerations, the Racal circuit is flawed in many parts;
it's anyway good enough for the counters it was designed for or the better
performance of other doublers will show up?
Best regards,
Andrea Baldoni
Andrea wrote:
the square-law characteristic of devices should be avoided, so the
configuration of the doubler must be some sort of "ideal" full wave rectifier
I disagree strongly with this, at least where push-push JFET doublers
are concerned.
If you look at the schematic Bruce posted on his site, which uses a
pair of J310 FETs driven into the pinch-off region, it runs the FETs
from 0 to about 21mA. My circuit, when using J310s, runs the FETs
from about 1mA to about 16mA. In both cases, when the FETs are
conducting they are operating as common-source linear amplifiers, NOT
as switches.
In either case, when one FET is drawing low (or zero) current, the
other one is drawing high current. The theoretical noise improvement
due to running the low-current FET past the pinch-off point is, in
practice, totally swamped by the noise from the other FET.
In order to realize a useful reduction of noise, the FETs would have
to switch hard, from "off" (beyond pinchoff) to "full on" (with
Vgs=0) -- but JFETs don't work like that, unless you drive the gates
hard with square waves (that is how commutating mixers such as the
ones designed by Ed Oxner and the later "H-mode" mixers work). See
below for a schematic of an Oxner mixer using a quad JFET (but note
that commutating mixers generally use MOSFETs).
When my circuit is normalized for 50 ohm output (by using a 4:1
transformer at the output -- which is the preferred method of driving
50 ohms with it) and the bias and drive are adjusted for the same
currents as Bruce's circuit, the models predict almost identical
noise from the two circuits. As a real-world check, I adjusted the
bias conditions and drive on my breadboard doubler to give FET
currents from 1 to about 22mA, and the measured noise decreased by a
fraction of a dB. (The spurious distortion products rose somewhat,
but not nearly as much as when one drives the FETs beyond pinch-off.)
So no, running the FETs in Class AB or B does NOT confer a material
noise advantage compared to running them in "barely Class A," as my
design does. It does, however, create an exponential explosion of
odd-order distortion products that must be removed if the circuit is
to be useful for time nuts purposes. So in my view, the "barely
Class A" push-push JFET doubler is clearly superior to its Class AB
or B cousin.
it's better to use diode-connected transistors like the 2N2222
* * *
matching is very important, so monolithic doubles or quadruples could be the
right choice, provided their other characteristics are compatible and the
substrate connection is not a problem
[NB: this applies to a mixer-based doubler, not a JFET push-push
doubler.] Again, this is a theoretical advantage that is easily
overshadowed in practice by the errors introduced by building one's
own diode DBM. It is not impossible to build a home-brew DBM that
performs as well as a good commercial DBM, but it is not easy,
either. Just a small imbalance due to unequal winding spacing on the
cores, small differences in stray capacitance, or geometric
differences due to the packaging of the transistors used can easily
create increased distortion products that are much worse than the 2
or 3dB reduction of noise you might realize. I'm not saying don't do
it, just that the chances of improving things without causing
collateral damage that is worse than the cure may not be high.
Best regards,
Charles
Not a good idea to use a bandpass filter even a crystal filter as such a filter has a relatively large phase shift tempco.The flicker phase noise of the filter crystal will degrade the output signal flicker phase noise significantly.Another issue is that the maximum crystal current will limit the maximum signal input to the crystal filter and thus degrade the output phase noise floor over that achievable using other approaches.
Bruce
On Wednesday, 28 January 2015 11:19 PM, Alberto di Bene <dibene@usa.net> wrote:
On 1/27/2015 11:57 PM, Bruce Griffiths wrote:
/The only viable solution is to use better filtering of the output of a switching multiplier./
What about filtering the doubler output with a 10 MHz xtal ?
73 Alberto I2PHD
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One issue is that to reduce flicker phase noise the 5MHz input signal output impedance should be sufficiently large to ensure that the JFET common gate input impedance is significantly smaller. ie there is significant series RF feedback in the JFET source circuit.
Bruce
On Sunday, 1 February 2015 2:57 PM, Charles Steinmetz <csteinmetz@yandex.com> wrote:
Andrea wrote:
the square-law characteristic of devices should be avoided, so the
configuration of the doubler must be some sort of "ideal" full wave rectifier
I disagree strongly with this, at least where push-push JFET doublers
are concerned.
If you look at the schematic Bruce posted on his site, which uses a
pair of J310 FETs driven into the pinch-off region, it runs the FETs
from 0 to about 21mA. My circuit, when using J310s, runs the FETs
from about 1mA to about 16mA. In both cases, when the FETs are
conducting they are operating as common-source linear amplifiers, NOT
as switches.
In either case, when one FET is drawing low (or zero) current, the
other one is drawing high current. The theoretical noise improvement
due to running the low-current FET past the pinch-off point is, in
practice, totally swamped by the noise from the other FET.
In order to realize a useful reduction of noise, the FETs would have
to switch hard, from "off" (beyond pinchoff) to "full on" (with
Vgs=0) -- but JFETs don't work like that, unless you drive the gates
hard with square waves (that is how commutating mixers such as the
ones designed by Ed Oxner and the later "H-mode" mixers work). See
below for a schematic of an Oxner mixer using a quad JFET (but note
that commutating mixers generally use MOSFETs).
When my circuit is normalized for 50 ohm output (by using a 4:1
transformer at the output -- which is the preferred method of driving
50 ohms with it) and the bias and drive are adjusted for the same
currents as Bruce's circuit, the models predict almost identical
noise from the two circuits. As a real-world check, I adjusted the
bias conditions and drive on my breadboard doubler to give FET
currents from 1 to about 22mA, and the measured noise decreased by a
fraction of a dB. (The spurious distortion products rose somewhat,
but not nearly as much as when one drives the FETs beyond pinch-off.)
So no, running the FETs in Class AB or B does NOT confer a material
noise advantage compared to running them in "barely Class A," as my
design does. It does, however, create an exponential explosion of
odd-order distortion products that must be removed if the circuit is
to be useful for time nuts purposes. So in my view, the "barely
Class A" push-push JFET doubler is clearly superior to its Class AB
or B cousin.
it's better to use diode-connected transistors like the 2N2222
* * *
matching is very important, so monolithic doubles or quadruples could be the
right choice, provided their other characteristics are compatible and the
substrate connection is not a problem
[NB: this applies to a mixer-based doubler, not a JFET push-push
doubler.] Again, this is a theoretical advantage that is easily
overshadowed in practice by the errors introduced by building one's
own diode DBM. It is not impossible to build a home-brew DBM that
performs as well as a good commercial DBM, but it is not easy,
either. Just a small imbalance due to unequal winding spacing on the
cores, small differences in stray capacitance, or geometric
differences due to the packaging of the transistors used can easily
create increased distortion products that are much worse than the 2
or 3dB reduction of noise you might realize. I'm not saying don't do
it, just that the chances of improving things without causing
collateral damage that is worse than the cure may not be high.
Best regards,
Charles
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On Sat, Jan 31, 2015 at 01:37:47PM -0500, Charles Steinmetz wrote:
Andrea wrote:
the square-law characteristic of devices should be avoided, so the
configuration of the doubler must be some sort of "ideal" full wave rectifier
I disagree strongly with this, at least where push-push JFET
doublers are concerned.
I see. This configuration is in effect a common gate B-class (or AB, or
"barely A") amplifier and the rectification is a side effect.
But, what is the advantage between it and a couple of diode-connected
transistors with a full A-class (more linear, so less spurs) amplifier in front
of it?
I know that the circuit originates at NIST and thus there surely IS an
advantage. Are it trading more spurs (that you can cancel out with filtering)
for less phase noise (that you cannot recover anymore)?
By the way, it's interesting that Richard Karlquist notice that 40MHz coming
from distortion and 40MHz coming from multiplication are in effect not
cleanly adding. Shouldn't happen the same degradation effect with the push-push
circuit, where 10Mhz coming from rectification superimpose with the ones
generated by nonlinearities in the active devices?
ones designed by Ed Oxner and the later "H-mode" mixers work). See
below for a schematic of an Oxner mixer using a quad JFET (but note
that commutating mixers generally use MOSFETs).
This is sort of "synchronous rectifier" the kind is used in SMPS.
So no, running the FETs in Class AB or B does NOT confer a material
noise advantage compared to running them in "barely Class A," as my
design does. It does, however, create an exponential explosion of
odd-order distortion products that must be removed if the circuit is
to be useful for time nuts purposes. So in my view, the "barely
Class A" push-push JFET doubler is clearly superior to its Class AB
or B cousin.
And Bruce added:
One issue is that to reduce flicker phase noise the 5MHz input signal output
impedance should be sufficiently large to ensure that the JFET common gate input
impedance is significantly smaller. ie there is significant series RF feedback
in the JFET source circuit.
Adding negative feedback linearize further the "barely Class A" amplifier; so,
it's good to sacrifice part of the gain of the push-push stage to reduce
flicker noise (and thus add less phase noise) and at the same time spurs.
If it's so, why use a nonlinear (or barely linear) gain stage to rectify?
Using just one stage means in general less phase noise output (but with
probably more spurs that can be filtered out), versus a more stage linear
amplifier (perhaps with strong negative feedblack) followed by a rectifier?
Best regards,
Andrea Baldoni
Andrea wrote:
I see. This configuration is in effect a common gate B-class (or AB, or
"barely A") amplifier and the rectification is a side effect.
But, what is the advantage between it and a couple of diode-connected
transistors with a full A-class (more linear, so less spurs)
amplifier in front
of it?
It is the rectification that causes the gross nonlinearities, not the
amplification. So no matter how linear an amplifier you make, the
diodes (or Class B or AB amplifier) will cause gross nonlinearities
that we do not want. Furthermore, transistors have both even- and
odd-order distortion products, while JFETs have predominantly
second-order products. So JFETs naturally tend to produce the second
harmonic, while transistors also produce the odd-order products we
are trying to avoid (as well as higher even-order products).
I know that the circuit originates at NIST and thus there surely IS an
advantage. Are it trading more spurs (that you can cancel out with filtering)
for less phase noise (that you cannot recover anymore)?
I do not know precisely how the NIST circuit is biased, and as far as
I know it is not general knowledge among time nuts -- so any
substantive response would be conjecture. I don't even know if NIST
still uses it. There are a few things to know -- NIST historically
settles on something that works well enough, then sticks with it for
a long time (until the phenomena they are trying to measure get
distinctly better than their instruments). NIST has lots of
considerations besides pure performance, such as power consumption
and fitting into old form factors, so they do not necessarily have
the best possible solutions, even when they have just designed the
next generation. So, what we know for sure is that the JFET
push-push doubler worked well enough for NIST's purposes when it was
designed. That does not mean improvements weren't possible.
Adding negative feedback linearize further the "barely Class A" amplifier; so,
it's good to sacrifice part of the gain of the push-push stage to reduce
flicker noise (and thus add less phase noise) and at the same time spurs.
But it is the natural second-order distortion of the JFETs that makes
it a particularly good way to build a push-push doubler. We don't
want to linearize it!
If it's so, why use a nonlinear (or barely linear) gain stage to rectify?
Using just one stage means in general less phase noise output (but with
probably more spurs that can be filtered out), versus a more stage linear
amplifier (perhaps with strong negative feedblack) followed by a rectifier?
The "barely Class A" push-push doubler does not rectify the signal --
it creates the second harmonic largely because of the device
characteristic. The design goal is to map the bias and input to the
portion of the FETs' characteristic curve that has the best fit to a
second-order transfer function, while at the same time holding noise
down below the noise budget. That is why medium-cutoff FETs like the
J111 and J310 are the best choices, not sharp-cutoff FETs like 2SK369
and BF862.
Best regards,
Charles
Whilst input frequency related spurs can be significantly reduced with a
suitable filter incorporating a sufficient number of series tuned traps plus
a low pass filter, phase noise once incurred cannot be reduced by such
means.
The ultimate measure of performance of the phase noise performance of a
frequency doubler is the input referred residual phase noise both for the
noise floor and the flicker phase regions.
The Wenzel JFET frequency doubler implementation (based on the NIST
design) has a specified input referred residual phase noise of
-155dBc/Hz @ 10Hz
-178dBc/Hz @100kHz.
for a 5MHz input signal.
http://www.wenzel.com/wp-content/uploads/LNHD.pdf
A BJT variant of the same circuit has an input referred residual phase noise
for a 5MHz input
-159dBc/Hz @ 10Hz offset
-180dBc/Hz @ 100KHz offset
If I have interpreted Adrian's measurements correctly see:
http://www.timeok.it/files/high_performance_frequency_doublerv13.pdf.
It would be interesting to compare these figures with the measured
residual phase noise of other frequency doublers such as Gerard's JFET
doubler using BF862's and the proposed near class A JFET based
frequency doubler.
Bruce
On Tuesday, January 27, 2015 02:25:54 PM Charles Steinmetz wrote:
Andrea wrote:
Now I have some 5MHz DOCXO. I have started to experiment with them
and I would like to build a frequency doubler.
* * *
By the way, I see that really many of the 10MHz reference out there,
are in
effect doubled 5MHz ones so build a doubler seems reasonable for me.
One thing to watch for is the 5MHz leakage component. If you are
going to use the 10MHz standard for time-nuts experiments, the 5MHz
component needs to be WAY down (< -80dBc) or you will get funny
periodic ripples in stability plots. Despite having two 5MHz traps,
one recently published design suppresses the 5MHz component only
about 52dB below the 10MHz output, and the 20MHz and 30MHz
components
are also only -50 to -55dB.
For this reason (and some others, see discussions over the last
several months in the archives) I prefer a doubler built with a
quadrature hybrid coupler and a balanced mixer. There is a write-up
here:
<http://www.ko4bb.com/manuals/download.php?file=02_GPS_Timing/4_App_
Notes_an
d_Articles/Frequency_doubler_quadrature_DBM.pdf>
I recently revived an old, stalled project to develop a JFET
push-push doubler for use at 5MHz (see schematic below).
FETs with very high transconductance and very small pinchoff voltage
(what a tube designer would call a "sharp cutoff" characteristic)
(e.g., 2SK369, BF862, etc.) are attractive on first look because they
can operate with lower conversion loss or even some conversion
gain. However, they are not well suited for doubler duty for two
reasons: (i) their characteristics have a very short range of
2nd-order curvature, so in order to keep noise down they must be
driven into regions of higher-order distortion and therefore generate
lots of spurious energy; and (ii) they are devilishly hard to match
well enough to suppress the input frequency feedthrough. Note that
you also need to put enough voltage on the FET drains to get them
well into the saturation region -- a Vcc of 5v is not enough. Again,
the penalty is lots of spurious energy. So, the lower conversion
loss of sharp-cutoff FETs is not the benefit it might at first appear
to be -- it is much easier to add gain after the doubler than to
remove unwanted spurious mixing products.
The design below uses medium-cutoff FETs and a Vcc of 15v (I found
that J111 and J310 work best and can be matched sufficiently with a
one-point match; 2N4416 and others also work, but are fussier and
would benefit from a 2- or 3-point match). At an input of 500mVrms,
their long 2nd-order characteristic is used efficiently to generate
10MHz with relatively little spurious energy.
I had no problem finding one or more FET pairs matched to within 1mV,
given 20 devices from the same lot (YMMV). With properly adjusted
traps at 5, 20, and 30MHz, all spurious responses were below
-80dBc. The inductors can be commercial RF parts with Q of 200 or so
(I used some high-quality through-hole RF inductors I had on hand --
I doubt any SMD inductors will work). The trap capacitors should be
C0G/NP0 ceramics for the bulk of the capacitance, plus very small
trimmers (I used 27pF, 27pF, and 100pF plus 0.2--6pF glass piston
trimmers). I wound the two transformers on Mix-61 toroid cores (each
winding is 20 turns on a FT37-61 core -- the inductance is a little
lower than called out). Mini-Circuits parts (or equivalents) may also
work.
Best regards,
Charles
Andrea wrote:
But, what is the advantage between it and a couple of diode-connected
transistors with a full A-class (more linear, so less spurs)
amplifier in front
of it?
If it's so, why use a nonlinear (or barely linear) gain stage to rectify?
Using just one stage means in general less phase noise output (but with
probably more spurs that can be filtered out), versus a more stage linear
amplifier (perhaps with strong negative feedblack) followed by a rectifier?
I replied:
The "barely Class A" push-push doubler does not rectify the signal
-- it creates the second harmonic because of the primarily
second-order transfer characteristics of the JFETs. The design goal
is to map the DC bias and the input signal to the portion of the
FETs' characteristic curve that has the best fit to a second-order
transfer function, while at the same time holding noise below the
design requirement.
Perhaps some pictures would be helpful (see below). Figure 1 (top)
shows an ideal full-wave rectified sine wave, similar to what is
produced by a full-wave diode rectifier, a bipolar transistor
push-push doubler, or a FET doubler driven into pinchoff (Class
B). Obviously, it is extremely rich in harmonics. The second
harmonic of the output (doubled) frequency is only 14dB below the
desired signal, and a series of even harmonics stretches as far as
the eye can see, diminishing only very slowly with increasing
harmonic number. (In practice, there will be a HF rolloff that makes
things slightly better. However, there will also be odd-order
components, which an ideal full-wave rectifier would not produce.)
Figure 2 (bottom) shows waveforms from the simulation of my "barely
Class A" push-push doubler, using a matched pair of J111 FETs (J310s
perform almost identically, with the appropriate change in the bias
resistor). I purposely introduced a 10mV gate voltage imbalance in
the simulation to model imperfect matching. The red and magenta
traces are the currents in the two FETs, showing a primarily
second-order transfer characteristic. When these currents are added
by the push-push connection and put through a 4:1 (turns ratio)
transformer into a 50 ohm load, the green trace results. This trace
shows the simulated raw output, without any traps. Obviously, this
is very much closer to a clean 10MHz signal than the rectified signal
in Figure 1.
The 5MHz component is ~40dB below the desired 10MHz signal. This
depends strongly on how well the FETs are matched and on the layout
and shielding. J111s or J310s from the same lot, matched to within
1mV, should do better than this (the 5MHz component from my
breadboard circuit is below -45dBc, without any traps). The other
visible distortion products, and their levels, are:
15MHz -75dBc
20MHz -45dBc
25MHz -100dBc
30MHz -75dBc
35MHz -100dBc (all figures are approximate).
The breadboard circuit performs similarly (the 15MHz component is
about 10dB lower from the breadboard, so I needed traps only at 5,
20, and 30MHz to get all spurious responses below -80dBc).
As I noted before, the "barely Class A" circuit is not materially
noisier than a FET push-push doubler that is run into Class AB or B,
but it has MUCH lower spurious outputs and, therefore, does not need
the sort of aggressive filtering the Class AB/B circuits need,
avoiding the increase in phase noise and other problems associated
with aggressive filters.
Best regards,
Charles
Whilst the output signal of the barely class A JFET amplifier has a lower
unwanted harmonic content and thus requires less filtering to achieve a
given suppression of unwanted harmonics and/or subharmonics, the
question of the flicker phase noise penalty incurred by the barely class A
amplifier approach remains unresolved.
Bruce
On Tuesday, February 03, 2015 01:12:41 AM Charles Steinmetz wrote:
Andrea wrote:
But, what is the advantage between it and a couple of diode-
connected
transistors with a full A-class (more linear, so less spurs)
amplifier in front
of it?
If it's so, why use a nonlinear (or barely linear) gain stage to rectify?
Using just one stage means in general less phase noise output (but
with
probably more spurs that can be filtered out), versus a more stage
linear
amplifier (perhaps with strong negative feedblack) followed by a
rectifier?
I replied:
The "barely Class A" push-push doubler does not rectify the signal
-- it creates the second harmonic because of the primarily
second-order transfer characteristics of the JFETs. The design goal
is to map the DC bias and the input signal to the portion of the
FETs' characteristic curve that has the best fit to a second-order
transfer function, while at the same time holding noise below the
design requirement.
Perhaps some pictures would be helpful (see below). Figure 1 (top)
shows an ideal full-wave rectified sine wave, similar to what is
produced by a full-wave diode rectifier, a bipolar transistor
push-push doubler, or a FET doubler driven into pinchoff (Class
B). Obviously, it is extremely rich in harmonics. The second
harmonic of the output (doubled) frequency is only 14dB below the
desired signal, and a series of even harmonics stretches as far as
the eye can see, diminishing only very slowly with increasing
harmonic number. (In practice, there will be a HF rolloff that makes
things slightly better. However, there will also be odd-order
components, which an ideal full-wave rectifier would not produce.)
Figure 2 (bottom) shows waveforms from the simulation of my "barely
Class A" push-push doubler, using a matched pair of J111 FETs (J310s
perform almost identically, with the appropriate change in the bias
resistor). I purposely introduced a 10mV gate voltage imbalance in
the simulation to model imperfect matching. The red and magenta
traces are the currents in the two FETs, showing a primarily
second-order transfer characteristic. When these currents are added
by the push-push connection and put through a 4:1 (turns ratio)
transformer into a 50 ohm load, the green trace results. This trace
shows the simulated raw output, without any traps. Obviously, this
is very much closer to a clean 10MHz signal than the rectified signal
in Figure 1.
The 5MHz component is ~40dB below the desired 10MHz signal. This
depends strongly on how well the FETs are matched and on the layout
and shielding. J111s or J310s from the same lot, matched to within
1mV, should do better than this (the 5MHz component from my
breadboard circuit is below -45dBc, without any traps). The other
visible distortion products, and their levels, are:
15MHz -75dBc
20MHz -45dBc
25MHz -100dBc
30MHz -75dBc
35MHz -100dBc (all figures are approximate).
The breadboard circuit performs similarly (the 15MHz component is
about 10dB lower from the breadboard, so I needed traps only at 5,
20, and 30MHz to get all spurious responses below -80dBc).
As I noted before, the "barely Class A" circuit is not materially
noisier than a FET push-push doubler that is run into Class AB or B,
but it has MUCH lower spurious outputs and, therefore, does not need
the sort of aggressive filtering the Class AB/B circuits need,
avoiding the increase in phase noise and other problems associated
with aggressive filters.
Best regards,
Charles