Whilst the output signal of the barely class A JFET amplifier has a
lower unwanted harmonic content and thus requires less filtering to
achieve a given suppression of unwanted harmonics and/or
subharmonics, the question of the flicker phase noise penalty
incurred by the barely class A amplifier approach remains unresolved.
I posted the resolution a few days ago.
As I said then, I adjusted the bias and input parameters of my
breadboard doubler to match the conditions under which the FETs are
operated in the doubler posted on your site, and measured the change
in noise (including in the flicker region). The noise decreased by a
fraction of a dB. Accordingly, I conclude that the barely class A
doubler's noise, including flicker noise, is within a fraction of a
dB of a Class AB doubler using the same FETs that you consider optimized.
I also explained then why this result should come as no surprise (one
FET in a Class AB or B doubler will not be contributing noise when it
is cut off -- but that coincides with the other FET being at or near
full current, so the total noise is dominated by the noise of the
full-current FET and the benefit due to the cut-off FET is insignificant).
There may be quieter FETs with lower flicker noise corners available
that have similar medium-cutoff characteristics and are, therefore,
suitable for this use -- but for the reasons I have given, I believe
that similar relative noise relationships between barely Class A and
Class AB doublers using such FETs would hold for them, as
well. NOTE: For anyone simulating JFET circuits, be aware that many
available JFET models do not model flicker noise at all, and many of
those that do are wildly inaccurate at simulating noise in the
flicker region. As always, there is no substitute for building and
measuring the circuit.
Best regards,
Charles
Bruce wrote:
>Whilst the output signal of the barely class A JFET amplifier has a
>lower unwanted harmonic content and thus requires less filtering to
>achieve a given suppression of unwanted harmonics and/or
>subharmonics, the question of the flicker phase noise penalty
>incurred by the barely class A amplifier approach remains unresolved.
I posted the resolution a few days ago.
As I said then, I adjusted the bias and input parameters of my
breadboard doubler to match the conditions under which the FETs are
operated in the doubler posted on your site, and measured the change
in noise (including in the flicker region). The noise decreased by a
fraction of a dB. Accordingly, I conclude that the barely class A
doubler's noise, including flicker noise, is within a fraction of a
dB of a Class AB doubler using the same FETs that you consider optimized.
I also explained then why this result should come as no surprise (one
FET in a Class AB or B doubler will not be contributing noise when it
is cut off -- but that coincides with the other FET being at or near
full current, so the total noise is dominated by the noise of the
full-current FET and the benefit due to the cut-off FET is insignificant).
There may be quieter FETs with lower flicker noise corners available
that have similar medium-cutoff characteristics and are, therefore,
suitable for this use -- but for the reasons I have given, I believe
that similar relative noise relationships between barely Class A and
Class AB doublers using such FETs would hold for them, as
well. NOTE: For anyone simulating JFET circuits, be aware that many
available JFET models do not model flicker noise at all, and many of
those that do are wildly inaccurate at simulating noise in the
flicker region. As always, there is no substitute for building and
measuring the circuit.
Best regards,
Charles
