O:TclTasksC:1850 - process run : Check Syntax is done. python /home/marius/source/uhd/fpga/usrp2/top/python/check_timing.py /home/marius/source/uhd/fpga/usrp2/top/USRP2/build/u2_rev3.twr Derived Constraint Report Derived Constraints for TS_clk_to_mac +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_clk_to_mac | 8.000ns| 5.987ns| 7.909ns| 0| 0| 0| 11618| | TS_clk125_ext_clk0 | 8.000ns| 1.316ns| N/A| 0| 0| 0| 0| | TS_clk125_ext_clk180 | 8.000ns| 1.316ns| N/A| 0| 0| 0| 0| | TS_clk125_int | 8.000ns| 7.909ns| N/A| 0| 0| 11618| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ Derived Constraints for TS_clk_fpga_p +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_clk_fpga_p | 10.000ns| 5.987ns| 10.168ns| 0| 5| 6| 1212679| | TS_dcm_out | 10.000ns| 10.168ns| N/A| 5| 0| 1123887| 0| | TS_clk_div | 20.000ns| 19.654ns| N/A| 0| 0| 88792| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ 1 constraint not met. Mainly I need the compatibility number 10, but the newest released build has 9. Could someone build me an FPGA image, that works, or help me fix this issue? Some nightly build here or something would do fine. I know it might be unstable. Best, Marius

s@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > Your question might better be directed to the OpenBTS mailing lists, rather than here. -- Marcus Leech Principal Investigator Shirleys Bay Radio Astronomy Consortium http://www.sbrac.org

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e polling loop takes 25 seconds to cycle through all the readings. The TT timetag and FC frequency control values have a high priority and are polled once a second. I could add the temperature to the high priority values, but that would really increase the time required to update all the values... I'll try that and see what happens. I could probably only add temperature to the high priority messages if the temp control pid is enabled. -------------- > Have you done a least-square fit to determine the sensitivity? Have you considered the LH approach to stabilizing it?

It looks like the PRS10 time tag processor / interpolator is rather crappy. I need to feed it the 1PPS from a 5071A to eliminate any temperature effects on the Tbolt. I did modify the message polling code to read the case temperature every second. That increased the time needed to get all the data values from the PRS10 to 35 seconds... a 10 second increase, You can only get around 5 values per second from the PRS10 and there are around 50 values it can report. If three of those 5 values per second are TT, FC, and AD10 that leaves room for getting 2 of those 50 values per second. ----------- > Have you done a least-square fit to determine the sensitivity?

her than 245.76 MSps. I don't own that device, nor use UHD4, but I guess one can build such image using [2]: ```bash cd $UHD_SOURCE/fpga/usrp3/top/x400/ rfnoc_image_builder -y ./x410_400_rfnoc_image_core.yml ``` And use the generated bitstream under ./build/ N.B.: I don't know if the bitstream is compatible with UHD-4.1 or only works with UHD-master. [1] https://files.ettus.com/manual/page_usrp_x4xx.html#x4xx_updating_fpga_types [2] https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0#Running_the_Image_Builder -- Cédric Hannotier