Merge branch 'maint'

Hi! I'm building an FPGA image for my USRP2s: λ ~/source/uhd/fpga/usrp2/top/USRP2/ master* git show commit 869e5ff110a56c597acff5e493e603eef2bde366 Merge: 6ca39ad c42c02f Author: Josh Blum <josh@joshknows.com> Date: Wed Apr 25 19:15:21 2012 -0700 Merge branch 'maint' When I make this I get into failed constraints Process "Check Syntax" failed INFO:TclTasksC:1850 - process run : Check Syntax is done. python /home/marius/source/uhd/fpga/usrp2/top/python/check_timing.py /home/marius/source/uhd/fpga/usrp2/top/USRP2/build/u2_rev3.twr Derived Constraint Report Derived Constraints for TS_clk_to_mac +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_clk_to_mac | 8.000ns| 5.987ns| 7.909ns| 0| 0| 0| 11618| | TS_clk125_ext_clk0 | 8.000ns| 1.316ns| N/A| 0| 0| 0| 0| | TS_clk125_ext_clk180 | 8.000ns| 1.316ns| N/A| 0| 0| 0| 0| | TS_clk125_int | 8.000ns| 7.909ns| N/A| 0| 0| 11618| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ Derived Constraints for TS_clk_fpga_p +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ | | Period | Actual Period | Timing Errors | Paths Analyzed | | Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------| | | | Direct | Derivative | Direct | Derivative | Direct | Derivative | +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ |TS_clk_fpga_p | 10.000ns| 5.987ns| 10.168ns| 0| 5| 6| 1212679| | TS_dcm_out | 10.000ns| 10.168ns| N/A| 5| 0| 1123887| 0| | TS_clk_div | 20.000ns| 19.654ns| N/A| 0| 0| 88792| 0| +-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+ 1 constraint not met. Mainly I need the compatibility number 10, but the newest released build has 9. Could someone build me an FPGA image, that works, or help me fix this issue? Some nightly build here or something would do fine. I know it might be unstable. Best, Marius

 Merge branch 'maint'

On 05/08/2012 03:36 AM, Marius wrote: > Hi! > > I'm building an FPGA image for my USRP2s: > > λ ~/source/uhd/fpga/usrp2/top/USRP2/ master* git show > commit 869e5ff110a56c597acff5e493e603eef2bde366 > Merge: 6ca39ad c42c02f > Author: Josh Blum <josh@joshknows.com> > Date: Wed Apr 25 19:15:21 2012 -0700 > > Merge branch 'maint' > > When I make this I get into failed constraints > > Process "Check Syntax" failed > INFO:TclTasksC:1850 - process run : Check Syntax is done. > python /home/marius/source/uhd/fpga/usrp2/top/python/check_timing.py > /home/marius/source/uhd/fpga/usrp2/top/USRP2/build/u2_rev3.twr > > What version of ise? I was using 12.1 for this build and I have known 13.1 to build it as well > > Mainly I need the compatibility number 10, but the newest released build has 9. > Could someone build me an FPGA image, that works, or help me fix this issue? > Some nightly build here or something would do fine. I know it might be unstable. > This feature has been merged onto the master branch for N200/N210, you can get images here: http://files.ettus.com/binaries/master_images/ -josh