Hello, I am trying to build multi channel transmitter and receiver using USRP E310. However I am new to FPGA programming, hence I am facing a lot of challenges in interfacing ZynQ board with the transceiver and filter banks in Vivado 2015.4. Is to possible to get few demo projects which might help me to understand the data flow in the simple transmitter and receiver application? Kindly share few useful documents which will help me to understand the above problem. *Thanks & Regards,* *Bhushan R.V. Pawar.*

Hi Bhushan, On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users <usrp-users@lists.ettus.com> wrote: > Hello, > > I am trying to build multi channel transmitter and receiver using USRP E310. all our code for E310 is open-source. Feel free to peruse our github. On the FPGA side you might wanna look at the usrp3/top/e300 subdirectory [1]. If you let us know what exactly you're trying to do, people can help you out easier. > However I am new to FPGA programming, hence I am facing a lot of challenges > in interfacing ZynQ board with the transceiver and filter banks in Vivado > 2015.4. > Is to possible to get few demo projects which might help me to understand > the data flow in the simple transmitter and receiver application? Kindly > share few useful documents which will help me to understand the above > problem. Again, all our code for E310 is open source (apart from Xilinx IP). Feel free to dig through the code. The filter bank settings are documented in the UHD manual [2]. Good luck, Moritz [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 [2] http://files.ettus.com/manual/page_usrp_e3x0.html

Dear Moritz, Thank you for the reply. I want to use E310 as multi channel transmitter and receiver and want to test it using signal generator and oscilloscope. I tried to import the code from usrp3/top/e300 subdirectory into Vivado 2015.4 but it is giving many errors when I try to synthesize it. Can you explain me step by step, how to work with E310. *Thanks !!* On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer <moritz.fischer@ettus.com> wrote: > Hi Bhushan, > > On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users > <usrp-users@lists.ettus.com> wrote: > > Hello, > > > > I am trying to build multi channel transmitter and receiver using USRP > E310. > > all our code for E310 is open-source. Feel free to peruse our github. > On the FPGA side you might wanna look at the usrp3/top/e300 subdirectory > [1]. > > If you let us know what exactly you're trying to do, people can help > you out easier. > > However I am new to FPGA programming, hence I am facing a lot of > challenges > > in interfacing ZynQ board with the transceiver and filter banks in Vivado > > 2015.4. > > Is to possible to get few demo projects which might help me to understand > > the data flow in the simple transmitter and receiver application? Kindly > > share few useful documents which will help me to understand the above > > problem. > > Again, all our code for E310 is open source (apart from Xilinx IP). > Feel free to dig through the code. > The filter bank settings are documented in the UHD manual [2]. > > Good luck, > > Moritz > > [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 > [2] http://files.ettus.com/manual/page_usrp_e3x0.html >

Hi, Have you also tried vivado forums? They can help more than what we can here... Plz post your errors. Recently started on vivado myself, and the only errors I got were from licensing issues for my FPGA. I have an X300 HTH, Nikos On Mon, Feb 15, 2016 at 12:54 PM, BHUSHAN PAWAR via USRP-users < usrp-users@lists.ettus.com> wrote: > Dear Moritz, > > Thank you for the reply. > > I want to use E310 as multi channel transmitter and receiver and want to > test it using signal generator and oscilloscope. > > I tried to import the code from usrp3/top/e300 subdirectory into Vivado > 2015.4 but it is giving many errors when I try to synthesize it. > > Can you explain me step by step, how to work with E310. > > > > > *Thanks !!* > > > > > On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer <moritz.fischer@ettus.com> > wrote: > >> Hi Bhushan, >> >> On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users >> <usrp-users@lists.ettus.com> wrote: >> > Hello, >> > >> > I am trying to build multi channel transmitter and receiver using USRP >> E310. >> >> all our code for E310 is open-source. Feel free to peruse our github. >> On the FPGA side you might wanna look at the usrp3/top/e300 subdirectory >> [1]. >> >> If you let us know what exactly you're trying to do, people can help >> you out easier. >> > However I am new to FPGA programming, hence I am facing a lot of >> challenges >> > in interfacing ZynQ board with the transceiver and filter banks in >> Vivado >> > 2015.4. >> > Is to possible to get few demo projects which might help me to >> understand >> > the data flow in the simple transmitter and receiver application? Kindly >> > share few useful documents which will help me to understand the above >> > problem. >> >> Again, all our code for E310 is open source (apart from Xilinx IP). >> Feel free to dig through the code. >> The filter bank settings are documented in the UHD manual [2]. >> >> Good luck, >> >> Moritz >> >> [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 >> [2] http://files.ettus.com/manual/page_usrp_e3x0.html >> > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

 Hi Bhushan,

 On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users
 <usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>>
 wrote:

 using USRP E310.

 all our code for E310 is open-source. Feel free to peruse our github.
 On the FPGA side you might wanna look at the usrp3/top/e300
 subdirectory [1].

 If you let us know what exactly you're trying to do, people can help
 you out easier.

 in Vivado

 understand

 application? Kindly

 above

 Again, all our code for E310 is open source (apart from Xilinx IP).
 Feel free to dig through the code.
 The filter bank settings are documented in the UHD manual [2].

 Good luck,

 Moritz

 [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300
 [2] http://files.ettus.com/manual/page_usrp_e3x0.html

Hi Pawar, first of all: for none of the things you say you want to use the E310 for you'd need to modify the FPGA image. Just use the stock image we ship. If you still want to modify it: There's the FPGA build guide to guide you through the FPGA build process: http://files.ettus.com/manual/page_usrp_e3x0.html http://files.ettus.com/manual/md_fpga.html Best regards, Marcus On 02/15/2016 11:54 AM, BHUSHAN PAWAR via USRP-users wrote: > Dear Moritz, > > Thank you for the reply. > > I want to use E310 as multi channel transmitter and receiver and want > to test it using signal generator and oscilloscope. > > I tried to import the code from usrp3/top/e300 subdirectory into > Vivado 2015.4 but it is giving many errors when I try to synthesize it. > > Can you explain me step by step, how to work with E310. > > > > *Thanks !! > * > > > > > On Thu, Feb 11, 2016 at 6:58 PM, Moritz Fischer > <moritz.fischer@ettus.com <mailto:moritz.fischer@ettus.com>> wrote: > > Hi Bhushan, > > On Thu, Feb 11, 2016 at 9:30 AM, BHUSHAN PAWAR via USRP-users > <usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com>> > wrote: > > Hello, > > > > I am trying to build multi channel transmitter and receiver > using USRP E310. > > all our code for E310 is open-source. Feel free to peruse our github. > On the FPGA side you might wanna look at the usrp3/top/e300 > subdirectory [1]. > > If you let us know what exactly you're trying to do, people can help > you out easier. > > However I am new to FPGA programming, hence I am facing a lot of challenges > > in interfacing ZynQ board with the transceiver and filter banks > in Vivado > > 2015.4. > > Is to possible to get few demo projects which might help me to > understand > > the data flow in the simple transmitter and receiver > application? Kindly > > share few useful documents which will help me to understand the > above > > problem. > > Again, all our code for E310 is open source (apart from Xilinx IP). > Feel free to dig through the code. > The filter bank settings are documented in the UHD manual [2]. > > Good luck, > > Moritz > > [1] https://github.com/EttusResearch/fpga/tree/master/usrp3/top/e300 > [2] http://files.ettus.com/manual/page_usrp_e3x0.html > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com