On 09/29/2018 02:20 PM, Arun kumar Verma wrote: > Hi > > Please find the screenshots as you have asked. One image is when we > are setting ref to internal but external not connected that time it is > clean and other images is when we are connecting external ref . > > Regards, > arun verma > Does the magnitude of this small spur diminish if you reduce the amplitude of your external reference? > > ------------------------------------------------------------------------ > *From:* Marcus D. Leech <mleech@ripnet.com> > *To:* Arun kumar Verma <arun.verma@eiwave.com>; > "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com> > *Sent:* Wednesday, 26 September 2018 11:56 PM > *Subject:* Re: [USRP-users] B205 External Reference issue > > On 09/26/2018 02:24 PM, Arun kumar Verma wrote: >>> Hi Marcus >>> >>> well I am connecting external ref of 10MHz on Ref Input SMA >>> connector and once I connect this and set my clock source for >>> external source then we are getting spurios, these spurs are low but >>> for AM,FM audio demodulation even Hz suprs can create probelem and >>> that is what we are facing. Right now what we using a VCXO of 50ppb >>> satbility and what we noticed that with the internal clock there was >>> a shift in frequency of about 5KHz at 3GHz input while with external >>> Ref shift was around 300Hz. Is it possible to switch off supply >>> manually for internal oscillator and board still works? >>> >>> Regards, >>> Arun Verma >> > Could you please post an image of the situation, showing the spur levels? > > > >> >> ------------------------------------------------------------------------ >> *From:* Marcus D. Leech via USRP-users <usrp-users@lists.ettus.com> >> <mailto:usrp-users@lists.ettus.com> >> *To:* usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com> >> *Sent:* Wednesday, 26 September 2018 9:15 PM >> *Subject:* Re: [USRP-users] B205 External Reference issue >> >> On 09/26/2018 02:42 AM, Arun kumar Verma via USRP-users wrote: >>> Hi >>> >>> We are using B205i-mini and we found that when I am sleclecting >>> external Ref using set_clock_source("ëxternal"); I am getting >>> intermodulation components in Hz. >>> I think supply for the internal oscillator is still on and it is not >>> compeletly shutting down. Is there any options to switch off the >>> suppy of ineternal oscillator through some API. >>> >>> Regards, >>> Arun Verma >>> >>> >> There is only one clock on the B205 -- a 40MHz VCXO. When you >> switch to "external", the FPGA implements a clock-steering >> "servo" that phase-locks that 40MHz clock to the external reference. >> >> You're probably seeing very low-level clock spurs that appear as a >> result of the servo algorithm. >> >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com> >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >> >> <https://www.avast.com/en-in/recommend?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail&utm_term=default3&tag=abba9460-2685-4c1f-847f-3d7d1f11e023> >> I’m protected online with Avast Free Antivirus. Get it here — it’s >> free forever. >> <https://www.avast.com/en-in/recommend?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail&utm_term=default3&tag=abba9460-2685-4c1f-847f-3d7d1f11e023> >> >> > > >

  From: Marcus D. Leech <mleech@ripnet.com>

    From: Marcus D. Leech <mleech@ripnet.com>

 Hi Marcus  

     From: Marcus D. Leech via USRP-users <usrp-users@lists.ettus.com>

On 09/26/2018 02:42 AM, Arun kumar Verma via USRP-users wrote:

 Hi  

I have tried that but it increases when i reduce amplitude , in fact for DC coupled ref i am getting best result. I have checked the schematic and in that if i remove R37 and R38 then my internal clock will disconnected but i am not sure whether board will work with only external clock or not. Can you verify this. I want to disconnect internal clock and want only external clock as there I am not getting any drift. Arun From: Marcus D. Leech <mleech@ripnet.com> To: Arun kumar Verma <arun.verma@eiwave.com>; "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com> Sent: Sunday, 30 September 2018 2:19 AM Subject: Re: [USRP-users] B205 External Reference issue On 09/29/2018 02:20 PM, Arun kumar Verma wrote: Hi Please find the screenshots as you have asked. One image is when we are setting ref to internal but external not connected that time it is clean and other images is when we are connecting external ref . Regards, arun verma Does the magnitude of this small spur diminish if you reduce the amplitude of your external reference? From: Marcus D. Leech <mleech@ripnet.com> To: Arun kumar Verma <arun.verma@eiwave.com>; "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com> Sent: Wednesday, 26 September 2018 11:56 PM Subject: Re: [USRP-users] B205 External Reference issue On 09/26/2018 02:24 PM, Arun kumar Verma wrote: Hi Marcus  well I am connecting external ref of 10MHz on Ref Input SMA connector and once I connect this and set my clock source for external source then we are getting spurios, these spurs are low but for AM,FM audio demodulation even Hz suprs can create probelem and that is what we are facing. Right now what we using a VCXO of 50ppb satbility and what we noticed that with the internal clock there was a shift in frequency of about 5KHz at 3GHz input while with external Ref shift was around 300Hz. Is it possible to switch off supply manually for internal oscillator and board still works? Regards, Arun Verma Could you please post an image of the situation, showing the spur levels? From: Marcus D. Leech via USRP-users <usrp-users@lists.ettus.com> To: usrp-users@lists.ettus.com Sent: Wednesday, 26 September 2018 9:15 PM Subject: Re: [USRP-users] B205 External Reference issue On 09/26/2018 02:42 AM, Arun kumar Verma via USRP-users wrote: Hi  We are using B205i-mini and we found that when I am sleclecting external Ref using set_clock_source("ëxternal"); I am getting intermodulation components in Hz. I think supply for the internal oscillator is still on and it is not compeletly shutting down. Is there any options to switch off the suppy of ineternal oscillator through some API.  Regards, Arun Verma There is only one clock on the B205 -- a 40MHz VCXO.   When you switch to "external", the FPGA implements a clock-steering   "servo" that phase-locks that 40MHz clock to the external reference. You're probably seeing very low-level clock spurs that appear as a result of the servo algorithm. _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com | | I’m protected online with Avast Free Antivirus. Get it here — it’s free forever. |

On 09/30/2018 03:55 AM, Arun kumar Verma wrote: > I have tried that but it increases when i reduce amplitude , in fact > for DC coupled ref i am getting best result. > > I have checked the schematic and in that if i remove R37 and R38 then > my internal clock will disconnected but i am not sure whether board > will work with only external clock or not. Can you verify this. I want > to disconnect internal clock and want only external clock as there I > am not getting any drift. > DO NOT DO THIS. > Arun > > > ------------------------------------------------------------------------ > *From:* Marcus D. Leech <mleech@ripnet.com> > *To:* Arun kumar Verma <arun.verma@eiwave.com>; > "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com> > *Sent:* Sunday, 30 September 2018 2:19 AM > *Subject:* Re: [USRP-users] B205 External Reference issue > > On 09/29/2018 02:20 PM, Arun kumar Verma wrote: >> Hi >> >> Please find the screenshots as you have asked. One image is when we >> are setting ref to internal but external not connected that time it >> is clean and other images is when we are connecting external ref . >> >> Regards, >> arun verma >> > Does the magnitude of this small spur diminish if you reduce the > amplitude of your external reference? > > > >> >> ------------------------------------------------------------------------ >> *From:* Marcus D. Leech <mleech@ripnet.com> <mailto:mleech@ripnet.com> >> *To:* Arun kumar Verma <arun.verma@eiwave.com> >> <mailto:arun.verma@eiwave.com>; "usrp-users@lists.ettus.com" >> <mailto:usrp-users@lists.ettus.com> <usrp-users@lists.ettus.com> >> <mailto:usrp-users@lists.ettus.com> >> *Sent:* Wednesday, 26 September 2018 11:56 PM >> *Subject:* Re: [USRP-users] B205 External Reference issue >> >> On 09/26/2018 02:24 PM, Arun kumar Verma wrote: >>>> Hi Marcus >>>> >>>> well I am connecting external ref of 10MHz on Ref Input SMA >>>> connector and once I connect this and set my clock source for >>>> external source then we are getting spurios, these spurs are low >>>> but for AM,FM audio demodulation even Hz suprs can create probelem >>>> and that is what we are facing. Right now what we using a VCXO of >>>> 50ppb satbility and what we noticed that with the internal clock >>>> there was a shift in frequency of about 5KHz at 3GHz input while >>>> with external Ref shift was around 300Hz. Is it possible to switch >>>> off supply manually for internal oscillator and board still works? >>>> >>>> Regards, >>>> Arun Verma >>> >> Could you please post an image of the situation, showing the spur >> levels? >> >> >> >>> >>> ------------------------------------------------------------------------ >>> *From:* Marcus D. Leech via USRP-users <usrp-users@lists.ettus.com> >>> <mailto:usrp-users@lists.ettus.com> >>> *To:* usrp-users@lists.ettus.com <mailto:usrp-users@lists.ettus.com> >>> *Sent:* Wednesday, 26 September 2018 9:15 PM >>> *Subject:* Re: [USRP-users] B205 External Reference issue >>> >>> On 09/26/2018 02:42 AM, Arun kumar Verma via USRP-users wrote: >>>> Hi >>>> >>>> We are using B205i-mini and we found that when I am sleclecting >>>> external Ref using set_clock_source("ëxternal"); I am getting >>>> intermodulation components in Hz. >>>> I think supply for the internal oscillator is still on and it is >>>> not compeletly shutting down. Is there any options to switch off >>>> the suppy of ineternal oscillator through some API. >>>> >>>> Regards, >>>> Arun Verma >>>> >>>> >>> There is only one clock on the B205 -- a 40MHz VCXO. When you >>> switch to "external", the FPGA implements a clock-steering >>> "servo" that phase-locks that 40MHz clock to the external reference. >>> >>> You're probably seeing very low-level clock spurs that appear as a >>> result of the servo algorithm. >>> >>> >>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com> >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >>> >>> <https://www.avast.com/en-in/recommend?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail&utm_term=default3&tag=abba9460-2685-4c1f-847f-3d7d1f11e023> >>> I’m protected online with Avast Free Antivirus. Get it here — it’s >>> free forever. >>> <https://www.avast.com/en-in/recommend?utm_medium=email&utm_source=link&utm_campaign=sig-email&utm_content=webmail&utm_term=default3&tag=abba9460-2685-4c1f-847f-3d7d1f11e023> >>> >>> >> >> >> > > >

Sylvain Munaut

Hi, I didn't see the screenshots (not posted to the list ?) But if absolute precision of the clock doesn't matter, you might be better off disabling the servo loop once it's "close enough". That will require fpga modifications to expose the refpll control though. Actually I think this would be a nice improvement in general for the b205 to have the DAC value exposed in UHD and allow to enable/disable the servo loop, just a thought :p Cheers, Sylvain Munaut

 Sylvain Munaut

Hm, there's beauty to that, but also there's beauty in not letting the oscillator drift of indefinitely after you've locked once. So, the classical fastlock at startup/loss of reference lock, and then increasingly reduced loop filter bandwidth would probably be even better. But that means relatively intrusive changes; you'd make `PFD_PERIOD_*` adaptive, you adapt the `err` clip boundaries, `lock_margin` and so on; the values used in b205_ref_pll are pretty certainly results of physical-reality-based verification¹. That's the point where you'd spend serious point characterizing the long-time behaviour of something that probably depends a lot on the characteristics of your clock source (unless that clock source is way superior to anything on the USRP). Also, that'd probably be the point where one would have to think about replacing the well-understood rational ratio PFD control loop with something more complex (and thus harder to make meet timing at acceptable resource usage and quantization loss) like an extended Kalman that can take the nonlinearities of the system into account. To be perfectly honest, I don't see either happen very soon. So, something like extending the state machine in b205_ref_pll to another state that has a larger threshold until it drops back into an adjusting state and adding a settings register to manually fiddle with the state would be the quick and potentially hazardous solution here, I'd guess. Best regards, Marcus ¹ a.k.a. experimentation On Sun, 2018-09-30 at 11:34 +0200, Sylvain Munaut via USRP-users wrote: > Hi, > > I didn't see the screenshots (not posted to the list ?) > > But if absolute precision of the clock doesn't matter, you might be > better off disabling the servo loop once it's "close enough". That > will require fpga modifications to expose the refpll control though. > Actually I think this would be a nice improvement in general for the > b205 to have the DAC value exposed in UHD and allow to enable/disable > the servo loop, just a thought :p > > Cheers, > > Sylvain Munaut > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Hi Well i want to synchronize two B205 mini radios with PPS and 10MHz external clock. Since only one Ref input port is available, is it possible to combine to signal and give it to Ref input or in B205 both synchronization not at all possible? Regards,Arun

On 10/08/2018 04:39 AM, Arun kumar Verma via USRP-users wrote: > Hi > > Well i want to synchronize two B205 mini radios with PPS and 10MHz > external clock. Since only one Ref input port is available, is it > possible to combine to signal and give it to Ref input or in B205 both > synchronization not at all possible? > > Regards, > Arun > The REF port on the B205 detects whether you're giving it 10MHz or 1PPS, and uses that to drive an internal clock servo that controls the on-board master clock. Unfortunately, due to the way that servo works (it's a DPLL), you cannot achieve tight phase synchronization between two or more B205s.

  From: Marcus D. Leech via USRP-users <usrp-users@lists.ettus.com>

Well if the phase difference is constant then i can manage it, but if it is random then I have a problem? From: Marcus D. Leech via USRP-users <usrp-users@lists.ettus.com> To: usrp-users@lists.ettus.com Sent: Monday, 8 October 2018 8:15 PM Subject: Re: [USRP-users] two B205 mini radios synchronization On 10/08/2018 04:39 AM, Arun kumar Verma via USRP-users wrote: Hi Well i want to synchronize two B205 mini radios with PPS and 10MHz external clock. Since only one Ref input port is available, is it possible to combine to signal and give it to Ref input or in B205 both synchronization not at all possible? Regards, Arun The REF port on the B205 detects whether you're giving it 10MHz or 1PPS, and uses that to drive an internal clock servo that controls the   on-board master clock. Unfortunately, due to the way that servo works (it's a DPLL), you cannot achieve tight phase synchronization between two or more B205s. _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

On 10/08/2018 11:02 AM, Arun kumar Verma wrote: > Well if the phase difference is constant then i can manage it, but if > it is random then I have a problem? There is high residual mutual phase-noise between B205s in this scenario. So, not useful for applications that require phase-coherence. > > > ------------------------------------------------------------------------ > *From:* Marcus D. Leech via USRP-users <usrp-users@lists.ettus.com> > *To:* usrp-users@lists.ettus.com > *Sent:* Monday, 8 October 2018 8:15 PM > *Subject:* Re: [USRP-users] two B205 mini radios synchronization > > On 10/08/2018 04:39 AM, Arun kumar Verma via USRP-users wrote: >> Hi >> >> Well i want to synchronize two B205 mini radios with PPS and 10MHz >> external clock. Since only one Ref input port is available, is it >> possible to combine to signal and give it to Ref input or in B205 >> both synchronization not at all possible? >> >> Regards, >> Arun >> > The REF port on the B205 detects whether you're giving it 10MHz or > 1PPS, and uses that to drive an internal clock servo that controls the > on-board master clock. > > Unfortunately, due to the way that servo works (it's a DPLL), you > cannot achieve tight phase synchronization between two or more B205s. > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com <mailto:USRP-users@lists.ettus.com> > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

 Sylvain

Hi, > Well if the phase difference is constant then i can manage it, but if it is random then I have a problem? > > There is high residual mutual phase-noise between B205s in this scenario. So, not useful for applications that require > phase-coherence. If you're ok with a bit of soldering ... I'm wondering if using one of the GPIO of the FPGA, connect it through a loop filter to the vctxo control pin, then inside the fpga, implement a phase detector (basically divide 40M / 4 and xor that with 10M ...) and output that. You would then use the DAC for the 'coarse' tuning, then be able to switch to a phase tracking mode when close enough. Just a thought ... Cheers, Sylvain PS: To make it clear, this will void your warranty, I'm not affiliated with ettus and this is definitely not any kind of official advice.