Hello everybody! I'd like to implement on USRP N hardware, an OFDM transceiver sending real-time video. I also want to implement a pre-equalization on the transmitter side using the channel state information estimate. I build the model using simulink, and I have several questions regarding what is the best to do to reach a real-time processing. I know that now, mathworks is supporting the UHD, but I wonder, since the model is quite complex if it can be executed on real-time. Furthermore, I need a full-duplex link, and this cannot be made with simulink as fas as I understood. The other point is the possibility to port the algorithms into the FPGA, but I am not an expert in VHDL, so one possibility is to use the HDL coder provided by mathworks. Then, I have several questions : 1) Since I need a full-duplex link, my understanding is that on the same Tx/Rx, for the receiver I do not need the frequency synchronization because the LO is the same for both Tx and Rx. Is that correct? 2) Do you think that the most reasonnable is to implement algorithms into the FPGA? 3) I do not understand the amount of places free that is given in percentage for the N200 and N210. How can I now, if it will be enough place for what I want to do? What do you recommend me, the N200 or N210? 4) If on transmitter side,  I put everything in the FPGA, even the OFDM modulation, do I need to change the communication layer with the host? or I can send raw data directly by putting the imaginary part to 0? 5) Since I have no skills in VHDL, do you think that using the HDL coder from mathworks will be satisfying? and how I can integrate the already existing part does is currently in the FPGA? is the existing FPGA code available for download? 6) I read that for the N200 the free version of ISE, but to change the FPGA into the N210, the full version is needed, why? 7) Does it exist some available tutorial to modify the FPGA (from the beginning to the generation of the file that will be on the flash card)? Thanks for answers! Henry

On Mon, Oct 10, 2011 at 8:23 AM, Henry Kopla <henry.kopla@yahoo.com> wrote: > Hello everybody! > > I'd like to implement on USRP N hardware, an OFDM transceiver sending > real-time video. I also want to implement a pre-equalization on the > transmitter side using the channel state information estimate. > I build the model using simulink, and I have several questions regarding > what is the best to do to reach a real-time processing. > I know that now, mathworks is supporting the UHD, but I wonder, since the > model is quite complex if it can be executed on real-time. Furthermore, I > need a full-duplex link, and this cannot be made with simulink as fas as I > understood. > The other point is the possibility to port the algorithms into the FPGA, but > I am not an expert in VHDL, so one possibility is to use the HDL coder > provided by mathworks. > Then, I have several questions : > 1) Since I need a full-duplex link, my understanding is that on the same > Tx/Rx, for the receiver I do not need the frequency synchronization because > the LO is the same for both Tx and Rx. Is that correct? If you are transmitting to a second device, and that device doesn't share the same reference source, you will have to implement some sort of synchronization between the two devices. > 2) Do you think that the most reasonnable is to implement algorithms into > the FPGA? You might consider using Gnuradio for your task. It will be much simpler than implementing the algorithms in the FPGA, and (depending on bandwidth required) should be fast enough to do video transmission. > 3) I do not understand the amount of places free that is given in percentage > for the N200 and N210. How can I now, if it will be enough place for what I > want to do? What do you recommend me, the N200 or N210? N210 has a larger FPGA, so if you are doing FPGA development the N210 is recommended. > 4) If on transmitter side,  I put everything in the FPGA, even the OFDM > modulation, do I need to change the communication layer with the host? or I > can send raw data directly by putting the imaginary part to 0? You can probably get away with doing the above. Or you could put your data in the real and imaginary parts and deinterleave them on the host. > 5) Since I have no skills in VHDL, do you think that using the HDL coder > from mathworks will be satisfying? and how I can integrate the already > existing part does is currently in the FPGA? is the existing FPGA code > available for download? Again I recommend using Gnuradio, unless you need very high bandwidth. The learning curve for Gnuradio is much smaller than for doing complex DSP operations in programmable logic. > 6) I read that for the N200 the free version of ISE, but to change the FPGA > into the N210, the full version is needed, why? Xilinx lets the free version work on their smaller FPGAs, but they require the paid version for their larger ones. N210 uses a larger FPGA. N200 uses one small enough to work with the free version. > 7) Does it exist some available tutorial to modify the FPGA (from the > beginning to the generation of the file that will be on the flash card)? Not really, although we can help answer specific questions on the list. > > Thanks for answers! > Henry > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

I am in the same situation and I am looking at the FPGA. I have tried compiling the FPGA designs from the uhd git clone that I did today, however I am getting an error. Process "Map" failed INFO:TclTasksC:1850 - process run : Generate Programming File is done. touch /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.bin python /home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr Traceback (most recent call last): File "/home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py", line 33, in <module> if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:]) File "/home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py", line 25, in print_timing_constraint_summary for line in open(twr_file).readlines(): IOError: [Errno 2] No such file or directory: '/home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr' make[1]: *** [bin] Error 1 make[1]: Leaving directory `/home/scap/Radio/uhd/fpga/usrp2/top/N2x0' make: *** [N200R3] Error 2 Does anyone know how I can get more information for diagnostics. I have installed a evaluation version of ISE 13.2 and am just running make on the fpga/usrp2/top directory. Any help would be appreciated. Also I think there will be a lot of interest in FPGA development as I have found that it will be needed for anything larger than 10MS/S on my computer. Perhaps we should start a wiki page and those of us working on this could start putting something together. - Scap On Mon, Oct 10, 2011 at 11:37 AM, Nick Foster <nick@ettus.com> wrote: > On Mon, Oct 10, 2011 at 8:23 AM, Henry Kopla <henry.kopla@yahoo.com> > wrote: > > Hello everybody! > > > > I'd like to implement on USRP N hardware, an OFDM transceiver sending > > real-time video. I also want to implement a pre-equalization on the > > transmitter side using the channel state information estimate. > > I build the model using simulink, and I have several questions regarding > > what is the best to do to reach a real-time processing. > > I know that now, mathworks is supporting the UHD, but I wonder, since the > > model is quite complex if it can be executed on real-time. Furthermore, I > > need a full-duplex link, and this cannot be made with simulink as fas as > I > > understood. > > The other point is the possibility to port the algorithms into the FPGA, > but > > I am not an expert in VHDL, so one possibility is to use the HDL coder > > provided by mathworks. > > Then, I have several questions : > > 1) Since I need a full-duplex link, my understanding is that on the same > > Tx/Rx, for the receiver I do not need the frequency synchronization > because > > the LO is the same for both Tx and Rx. Is that correct? > > If you are transmitting to a second device, and that device doesn't > share the same reference source, you will have to implement some sort > of synchronization between the two devices. > > > 2) Do you think that the most reasonnable is to implement algorithms into > > the FPGA? > > You might consider using Gnuradio for your task. It will be much > simpler than implementing the algorithms in the FPGA, and (depending > on bandwidth required) should be fast enough to do video transmission. > > > 3) I do not understand the amount of places free that is given in > percentage > > for the N200 and N210. How can I now, if it will be enough place for what > I > > want to do? What do you recommend me, the N200 or N210? > > N210 has a larger FPGA, so if you are doing FPGA development the N210 > is recommended. > > > 4) If on transmitter side, I put everything in the FPGA, even the OFDM > > modulation, do I need to change the communication layer with the host? or > I > > can send raw data directly by putting the imaginary part to 0? > > You can probably get away with doing the above. Or you could put your > data in the real and imaginary parts and deinterleave them on the > host. > > > 5) Since I have no skills in VHDL, do you think that using the HDL coder > > from mathworks will be satisfying? and how I can integrate the already > > existing part does is currently in the FPGA? is the existing FPGA code > > available for download? > > Again I recommend using Gnuradio, unless you need very high bandwidth. > The learning curve for Gnuradio is much smaller than for doing complex > DSP operations in programmable logic. > > > 6) I read that for the N200 the free version of ISE, but to change the > FPGA > > into the N210, the full version is needed, why? > > Xilinx lets the free version work on their smaller FPGAs, but they > require the paid version for their larger ones. N210 uses a larger > FPGA. N200 uses one small enough to work with the free version. > > > 7) Does it exist some available tutorial to modify the FPGA (from the > > beginning to the generation of the file that will be on the flash card)? > > Not really, although we can help answer specific questions on the list. > > > > > Thanks for answers! > > Henry > > _______________________________________________ > > USRP-users mailing list > > USRP-users@lists.ettus.com > > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > > > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >

Jeff, I'm getting this same error. Did you ever obtain a solution? Thanks, Steve On Mon, Oct 10, 2011 at 12:55 PM, Jeff Scaparra <Jeff@scaparra.com> wrote: > I am in the same situation and I am looking at the FPGA. I have tried > compiling the FPGA designs from the uhd git clone that I did today, however > I am getting an error. > > Process "Map" failed > INFO:TclTasksC:1850 - process run : Generate Programming File is done. > touch /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.bin > python /home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py > /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr > Traceback (most recent call last): > File "/home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py", line > 33, in <module> > if __name__=='__main__': map(print_timing_constraint_summary, > sys.argv[1:]) > File "/home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py", line > 25, in print_timing_constraint_summary > for line in open(twr_file).readlines(): > IOError: [Errno 2] No such file or directory: > '/home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr' > make[1]: *** [bin] Error 1 > make[1]: Leaving directory `/home/scap/Radio/uhd/fpga/usrp2/top/N2x0' > make: *** [N200R3] Error 2 > > Does anyone know how I can get more information for diagnostics. I have > installed a evaluation version of ISE 13.2 and am just running make on the > fpga/usrp2/top directory. > > Any help would be appreciated. Also I think there will be a lot of > interest in FPGA development as I have found that it will be needed for > anything larger than 10MS/S on my computer. Perhaps we should start a wiki > page and those of us working on this could start putting something > together. > > - Scap > >

Which flavor of USRP are you building for and using which ISE version pls? On May 9, 2012, at 12:19 PM, Steve Peters wrote: > Jeff, > > I'm getting this same error. Did you ever obtain a solution? > > Thanks, > Steve > > On Mon, Oct 10, 2011 at 12:55 PM, Jeff Scaparra <Jeff@scaparra.com> wrote: > I am in the same situation and I am looking at the FPGA. I have tried compiling the FPGA designs from the uhd git clone that I did today, however I am getting an error. > > Process "Map" failed > INFO:TclTasksC:1850 - process run : Generate Programming File is done. > touch /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.bin > python /home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr > Traceback (most recent call last): > File "/home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py", line 33, in <module> > if __name__=='__main__': map(print_timing_constraint_summary, sys.argv[1:]) > File "/home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py", line 25, in print_timing_constraint_summary > for line in open(twr_file).readlines(): > IOError: [Errno 2] No such file or directory: '/home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr' > make[1]: *** [bin] Error 1 > make[1]: Leaving directory `/home/scap/Radio/uhd/fpga/usrp2/top/N2x0' > make: *** [N200R3] Error 2 > > Does anyone know how I can get more information for diagnostics. I have installed a evaluation version of ISE 13.2 and am just running make on the fpga/usrp2/top directory. > > Any help would be appreciated. Also I think there will be a lot of interest in FPGA development as I have found that it will be needed for anything larger than 10MS/S on my computer. Perhaps we should start a wiki page and those of us working on this could start putting something together. > > - Scap > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

N210 rev3 and rev4 (have both, tried both, got the same error for both). ISE 14.1, just came out yesterday I believe. Maybe upgrading was a mistake. I've gotten it to work before with 13.2 on a completely different setup. On Wed, May 9, 2012 at 2:51 PM, Ian Buckley <ianb@ionconcepts.com> wrote: > Which flavor of USRP are you building for and using which ISE version pls? > > On May 9, 2012, at 12:19 PM, Steve Peters wrote: > > Jeff, > > I'm getting this same error. Did you ever obtain a solution? > > Thanks, > Steve > > On Mon, Oct 10, 2011 at 12:55 PM, Jeff Scaparra <Jeff@scaparra.com> wrote: > >> I am in the same situation and I am looking at the FPGA. I have tried >> compiling the FPGA designs from the uhd git clone that I did today, however >> I am getting an error. >> >> Process "Map" failed >> INFO:TclTasksC:1850 - process run : Generate Programming File is done. >> touch /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.bin >> python /home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py >> /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr >> Traceback (most recent call last): >> File "/home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py", line >> 33, in <module> >> if __name__=='__main__': map(print_timing_constraint_summary, >> sys.argv[1:]) >> File "/home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py", line >> 25, in print_timing_constraint_summary >> for line in open(twr_file).readlines(): >> IOError: [Errno 2] No such file or directory: >> '/home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr' >> make[1]: *** [bin] Error 1 >> make[1]: Leaving directory `/home/scap/Radio/uhd/fpga/usrp2/top/N2x0' >> make: *** [N200R3] Error 2 >> >> Does anyone know how I can get more information for diagnostics. I have >> installed a evaluation version of ISE 13.2 and am just running make on the >> fpga/usrp2/top directory. >> >> Any help would be appreciated. Also I think there will be a lot of >> interest in FPGA development as I have found that it will be needed for >> anything larger than 10MS/S on my computer. Perhaps we should start a wiki >> page and those of us working on this could start putting something >> together. >> >> - Scap >> >> _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > >

Turns out this is probably a licensing issue. I had a node-locked license tied to my WLAN card, and the license manager was reading the Ethernet LAN MAC. When ISE wouldn't build a certain part, the make file kept executing until it failed somewhere further down the line. I really appreciate the effort Ian. Steve On Wed, May 9, 2012 at 3:24 PM, Steve Peters <stevenpeters@gmail.com> wrote: > N210 rev3 and rev4 (have both, tried both, got the same error for both). > ISE 14.1, just came out yesterday I believe. Maybe upgrading was a > mistake. I've gotten it to work before with 13.2 on a completely different > setup. > > > On Wed, May 9, 2012 at 2:51 PM, Ian Buckley <ianb@ionconcepts.com> wrote: > >> Which flavor of USRP are you building for and using which ISE version pls? >> >> On May 9, 2012, at 12:19 PM, Steve Peters wrote: >> >> Jeff, >> >> I'm getting this same error. Did you ever obtain a solution? >> >> Thanks, >> Steve >> >> On Mon, Oct 10, 2011 at 12:55 PM, Jeff Scaparra <Jeff@scaparra.com>wrote: >> >>> I am in the same situation and I am looking at the FPGA. I have tried >>> compiling the FPGA designs from the uhd git clone that I did today, however >>> I am getting an error. >>> >>> Process "Map" failed >>> INFO:TclTasksC:1850 - process run : Generate Programming File is done. >>> touch /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.bin >>> python /home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py >>> /home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr >>> Traceback (most recent call last): >>> File "/home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py", >>> line 33, in <module> >>> if __name__=='__main__': map(print_timing_constraint_summary, >>> sys.argv[1:]) >>> File "/home/scap/Radio/uhd/fpga/usrp2/top/python/check_timing.py", >>> line 25, in print_timing_constraint_summary >>> for line in open(twr_file).readlines(): >>> IOError: [Errno 2] No such file or directory: >>> '/home/scap/Radio/uhd/fpga/usrp2/top/N2x0/build-N200R3/u2plus.twr' >>> make[1]: *** [bin] Error 1 >>> make[1]: Leaving directory `/home/scap/Radio/uhd/fpga/usrp2/top/N2x0' >>> make: *** [N200R3] Error 2 >>> >>> Does anyone know how I can get more information for diagnostics. I have >>> installed a evaluation version of ISE 13.2 and am just running make on the >>> fpga/usrp2/top directory. >>> >>> Any help would be appreciated. Also I think there will be a lot of >>> interest in FPGA development as I have found that it will be needed for >>> anything larger than 10MS/S on my computer. Perhaps we should start a wiki >>> page and those of us working on this could start putting something >>> together. >>> >>> - Scap >>> >>> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >> >