In a message dated 12/10/2007 13:16:38 Pacific Standard Time,
tractorb@ihug.co.nz writes:

Hi Dave,

http://www.ecliptek.com/tech/Vig-tutorial_8.5.1.2_files/frame.htm
(http://www.ecliptek.com/tech/Vig-tutorial_8.5.1.2_files/frame.htm)

this is the one I have been reading, impossible to print with IE6.

Same file is on the IEEE site as well.

Thanks everyone for the help!
bye,
Said

**************************************See AOL's top rated recipes
(http://food.aol.com/top-rated-recipes?NCID=aoltop00030000000004)

xaos wrote:

George

In the JFET frequency doubler:

1. Surely the 50 ohms should be is series with the the voltage source V3
   for the simulation?

2. Usually a 1:4 impedance ratio step up transformer on the input is
   about right with a similar transformer used to step down the output
   (perhaps an even higher impedance ratio transformer (8:1, 9:1?? may be
   better). The maximum turns ratio depends somewhat on the maximum
   allowable drain voltage swing which in turn is limited by the drain
   supply voltage.

In the voltage offset circuit:

1. The junction of R9 and R12 should be connected to the offset source
   (+5V??).

I dont understand what the 7812 does in this circuit.

Isolation amplifier looks OK.

Bruce

Bruce Griffiths wrote:

George

The LS840 series FET Idss is a little on the low side for this application.
Something equivalent to a matched pair of J310's would be better suited
to this application.
The higher Idss of such JFETs allows a larger amplitude second harmonic
output.

Bruce

xaos wrote:

George

The Fury EFC output range is [0, +5V]
The 10811A, 10544A have an EFC range of [-5V, +5V]
other OCXOs may have an EFC input range of [-10V ,0V], [0,+10V], [-10V,
+10V] or even [+2V, +8V] etc.

If the  circuit is changed so that R1 = R10 = 20K then

Range
[-10V, 0V]  U3A +ve input = 0 V.
[-5V, +5V]  U3A +ve input = +2.5V.
[0V, +10V]  U3A +ve input = +5V.
for a [-10V, +10V] range then R1=R10= 40K, U3A +ve input = +5V.
To check correct operation vary the Fury EFC output from 0 to 5V with
the desired offset at U3 +ve input.

Bruce

xaos wrote:

George

A more versatile EFC circuit that allows independent adjustment of EFC
span and offset is possible if an additional opamp is used.
A 2x differential amplifier translates the Fury EFC output to either
{-10V, 0V] or [0V, +10V] depending on its input connections,  a second
opamp inverts a  +5Vreference to produce a -5V source offset source, and
a third opamp configured as an inverting opamp scales the EFC range and
adds it to the offset to produce the required EFC range to suit the OCXO
in use. An OCXO  EFC range anywhere between -10V and + 10V can be
accommodated by selecting a couple of resistors  combined with a set of
jumpers.
If you want the circuit schematic I can produce it by around 1300 UTC
tomorrow.

Bruce

Bruce Griffiths wrote:

Correct. I did a cut and paste "without rotate" there.

I will re-run with the this in mind and will repost.

This is what I didn't get about the original circuit.  I was scratching
my head as to the purpose of a variable R9 when
the only value that made sense was when it was set to the "0" position.

It was there in the original circuit so I modeled accordingly. Actually
I ran some simulations with PS voltage variation
to see the effect as well. In that case I removed the 7812.

This is a very nice design and the AC analysis shows a bandpass around
10 MHz with 20 MHz BW.

The only issue I see there is that it needs 50 parts of 6 different values.

This might be difficult to implement on a small board and would be prone
to error for people trying to
assemble their own board.

The way I see the final product is a bare board and possibly a kit. It
has to be easy to assemble and minimize
errors.

Actually, I was looking at the isolation amplifier provided in the C.M.
Felton Paper:

http://www.darksmile.net/ee/Superimposing_Low-Phase-Noise_Low-Drift_Instrumentation_Techniques_On_RF_Design.pdf

It is relatively simple and would use similar devices as the Frequency
doubler.

I will upload more info as I compile it.

George

xaos wrote:

The idea is that the FETs are not operated in the square law region but
are actually switched off alternately so that the combined drain current
waveform is a rectified sinewave with a small dc offset.
With a well balanced circuit the odd harmonic amplitudes (including the
fundamental) at the output will be small with the 20MHz 4th harmonic of
the fundamental being the largest component.
Achieving low distortion isnt the aim, but achieving low phase noise is.
Any residual harmonics and subharmonics can be removed with tuned
circuit traps (dont use a high Q bandpass filter as it will inevitably
have a high phase shift tempco and may add flicker phase noise depending
on the components used). A relatively broadband low pass filter
contributes little phase shift (and associated flicker phase noise as
well as little phase shift tempco) at 10MHz as do a series of relatively
high Q LC traps. High performance is rarely achieved by the
simplest/obvious solution.
If you have difficulty finding suitable JFETs a high impedance bipolar
junction transistor (BJT) implementation is also possible however
biasing is a little trickier and requires a couple of extra BJTs to
ensure reasonable thermal stability of the bias currents.

The trouble with this design is that it has a low input impedance and
thus is unsuitable for OCXOs that require a high impedance load (eg 10544A).
Its gain isnt adjustable and its difficult to obtain suitable dual JFETS
(you would have to use a couple of J310's to achieve similar performance
since U431 isnt readily obtainable, the LS840 is definitely unsuitable
as its minimum Idss isnt high enough ), it also has relatively low
reverse isolation. Simplicity isnt the key to high performance.