Dear all, If I want to insert an IP core into the fpga, like a block ram, what is the right way of doing it? Should I create a folder under /usrp3/top/x300/ip, with .xci file and Makefile.inc in it, then just instantiate it in the source code. Can it work? Thanks, Zhihong

This very much sounds like you should actually be using RF Network On Chip, which has the functionality of offering you a clear API within which you can implement your functionality[1][2]. However, "Block RAM" is not a type of IP, but a piece of in-silicon RAM hardware; or are you specifically referring to Xilinx's BRAM IP core, which (as far as I can tell) doesn't apply to the Kintex7 in the X3x0? So: what is it that you want to do with the RAM? Best regards, Marcus [1] https://github.com/EttusResearch/uhd/wiki/RFNoC:--Specification [2] http://www.ettus.com/blog/2015/06/rfnoc-for-high-performance-sdr On 01/29/2016 03:48 AM, Zhihong Luo via USRP-users wrote: > Dear all, > > If I want to insert an IP core into the fpga, like a block ram, what > is the right way of doing it? > > Should I create a folder under /usrp3/top/x300/ip, with .xci file and > Makefile.inc in it, then just instantiate it in the source code. Can > it work? > > Thanks, > Zhihong > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

Hi Marcus, Thank you for the information regarding RFNoC. I am referring to the Block Memory Generator of the Xilinx, which should apply to Kintex 7. The thing I want to do is on TX side, I want it to periodically send data from the sample data I put in the ram in advance. On RX side I want the RAM to serve like a buffer, since I only accept signal periodically. I can first put the captured data in the ram first, then send it back to PC in a rather slow rate. Moreover, can we use the usrp sink to receive signal periodically? Thanks. Zhihong Luo 2016年1月29日星期五，Marcus Müller <usrp-users@lists.ettus.com> 写道： > This very much sounds like you should actually be using RF Network On > Chip, which has the functionality of offering you a clear API within which > you can implement your functionality[1][2]. > > However, "Block RAM" is not a type of IP, but a piece of in-silicon RAM > hardware; or are you specifically referring to Xilinx's BRAM IP core, which > (as far as I can tell) doesn't apply to the Kintex7 in the X3x0? > So: what is it that you want to do with the RAM? > > Best regards, > Marcus > > [1] https://github.com/EttusResearch/uhd/wiki/RFNoC:--Specification > [2] http://www.ettus.com/blog/2015/06/rfnoc-for-high-performance-sdr > > On 01/29/2016 03:48 AM, Zhihong Luo via USRP-users wrote: > > Dear all, > > If I want to insert an IP core into the fpga, like a block ram, what is > the right way of doing it? > > Should I create a folder under /usrp3/top/x300/ip, with .xci file and > Makefile.inc in it, then just instantiate it in the source code. Can it > work? > > Thanks, > Zhihong > > > _______________________________________________ > USRP-users mailing listUSRP-users@lists.ettus.com <javascript:_e(%7B%7D,'cvml','USRP-users@lists.ettus.com');>http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > >

Sorry, typo, it should be usrp source. 2016年1月29日星期五，Zhihong Luo <zhluo@umich.edu> 写道： > Hi Marcus, > > Thank you for the information regarding RFNoC. > > I am referring to the Block Memory Generator of the Xilinx, which should > apply to Kintex 7. The thing I want to do is on TX side, I want it to > periodically send data from the sample data I put in the ram in advance. On > RX side I want the RAM to serve like a buffer, since I only accept signal > periodically. I can first put the captured data in the ram first, then send > it back to PC in a rather slow rate. > > Moreover, can we use the usrp sink to receive signal periodically? > > Thanks. > Zhihong Luo > > 2016年1月29日星期五，Marcus Müller <usrp-users@lists.ettus.com > <javascript:_e(%7B%7D,'cvml','usrp-users@lists.ettus.com');>> 写道： > >> This very much sounds like you should actually be using RF Network On >> Chip, which has the functionality of offering you a clear API within which >> you can implement your functionality[1][2]. >> >> However, "Block RAM" is not a type of IP, but a piece of in-silicon RAM >> hardware; or are you specifically referring to Xilinx's BRAM IP core, which >> (as far as I can tell) doesn't apply to the Kintex7 in the X3x0? >> So: what is it that you want to do with the RAM? >> >> Best regards, >> Marcus >> >> [1] https://github.com/EttusResearch/uhd/wiki/RFNoC:--Specification >> [2] http://www.ettus.com/blog/2015/06/rfnoc-for-high-performance-sdr >> >> On 01/29/2016 03:48 AM, Zhihong Luo via USRP-users wrote: >> >> Dear all, >> >> If I want to insert an IP core into the fpga, like a block ram, what is >> the right way of doing it? >> >> Should I create a folder under /usrp3/top/x300/ip, with .xci file and >> Makefile.inc in it, then just instantiate it in the source code. Can it >> work? >> >> Thanks, >> Zhihong >> >> >> _______________________________________________ >> USRP-users mailing listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >>

 Hi Marcus,

 Thank you for the information regarding RFNoC.

 I am referring to the Block Memory Generator of the Xilinx, which
 should apply to Kintex 7. The thing I want to do is on TX side, I
 want it to periodically send data from the sample data I put in
 the ram in advance. On RX side I want the RAM to serve like a
 buffer, since I only accept signal periodically. I can first put
 the captured data in the ram first, then send it back to PC in a
 rather slow rate.

 Moreover, can we use the usrp sink to receive signal periodically?

 Thanks.
 Zhihong Luo 

 2016年1月29日星期五，Marcus Müller <usrp-users@lists.ettus.com
 <javascript:_e(%7B%7D,'cvml','usrp-users@lists.ettus.com');>> 写道：

     This very much sounds like you should actually be using RF
     Network On Chip, which has the functionality of offering you a
     clear API within which you can implement your functionality[1][2].

     However, "Block RAM" is not a type of IP, but a piece of
     in-silicon RAM hardware; or are you specifically referring to
     Xilinx's BRAM IP core, which (as far as I can tell) doesn't
     apply to the Kintex7 in the X3x0?
     So: what is it that you want to do with the RAM?

     Best regards,
     Marcus

     [1]
     https://github.com/EttusResearch/uhd/wiki/RFNoC:--Specification
     [2]
     http://www.ettus.com/blog/2015/06/rfnoc-for-high-performance-sdr

     On 01/29/2016 03:48 AM, Zhihong Luo via USRP-users wrote:

     Dear all,

     If I want to insert an IP core into the fpga, like a block
     ram, what is the right way of doing it?

     Should I create a folder under /usrp3/top/x300/ip, with .xci
     file and Makefile.inc in it, then just instantiate it in the
     source code. Can it work?

     Thanks,
     Zhihong


     _______________________________________________
     USRP-users mailing list
     USRP-users@lists.ettus.com
     http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

I'd say the easiest way to do that would be to continously receive samples on the PC and just drop them when you don't need them. I don't know how much buffering you need, but: if you use one of the the FPGA images that don't use the external RAM, you can "just" use a memory controller interface, wrap it in an RFNoC block and implement that as sample source. The most interesting part here will be how you control the Radio frontend -- that's classically done from the host. Best regards, Marcus On 01/29/2016 03:29 PM, Zhihong Luo wrote: > Sorry, typo, it should be usrp source. > > 2016年1月29日星期五，Zhihong Luo <zhluo@umich.edu > <mailto:zhluo@umich.edu>> 写道： > > Hi Marcus, > > Thank you for the information regarding RFNoC. > > I am referring to the Block Memory Generator of the Xilinx, which > should apply to Kintex 7. The thing I want to do is on TX side, I > want it to periodically send data from the sample data I put in > the ram in advance. On RX side I want the RAM to serve like a > buffer, since I only accept signal periodically. I can first put > the captured data in the ram first, then send it back to PC in a > rather slow rate. > > Moreover, can we use the usrp sink to receive signal periodically? > > Thanks. > Zhihong Luo > > 2016年1月29日星期五，Marcus Müller <usrp-users@lists.ettus.com > <javascript:_e(%7B%7D,'cvml','usrp-users@lists.ettus.com');>> 写道： > > This very much sounds like you should actually be using RF > Network On Chip, which has the functionality of offering you a > clear API within which you can implement your functionality[1][2]. > > However, "Block RAM" is not a type of IP, but a piece of > in-silicon RAM hardware; or are you specifically referring to > Xilinx's BRAM IP core, which (as far as I can tell) doesn't > apply to the Kintex7 in the X3x0? > So: what is it that you want to do with the RAM? > > Best regards, > Marcus > > [1] > https://github.com/EttusResearch/uhd/wiki/RFNoC:--Specification > [2] > http://www.ettus.com/blog/2015/06/rfnoc-for-high-performance-sdr > > On 01/29/2016 03:48 AM, Zhihong Luo via USRP-users wrote: >> Dear all, >> >> If I want to insert an IP core into the fpga, like a block >> ram, what is the right way of doing it? >> >> Should I create a folder under /usrp3/top/x300/ip, with .xci >> file and Makefile.inc in it, then just instantiate it in the >> source code. Can it work? >> >> Thanks, >> Zhihong >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >

Hi Marcus, The RFNoC seems pretty complicated to me since I need to build a new path between host and FPGA. And as you said, controlling the radio frontend may be a problem. Can I modify the fpga (run_rx), so that fpga transmits to usrp source when it is not sampling? If so, I think putting sampling data in the RAM then sends it back while the usrp is not sampling may be easier. Thanks, Zhihong On Fri, Jan 29, 2016 at 11:50 PM, Marcus Müller <marcus.mueller@ettus.com> wrote: > I'd say the easiest way to do that would be to continously receive samples > on the PC and just drop them when you don't need them. > I don't know how much buffering you need, but: if you use one of the the > FPGA images that don't use the external RAM, you can "just" use a memory > controller interface, wrap it in an RFNoC block and implement that as > sample source. The most interesting part here will be how you control the > Radio frontend -- that's classically done from the host. > > Best regards, > Marcus > > > On 01/29/2016 03:29 PM, Zhihong Luo wrote: > > Sorry, typo, it should be usrp source. > > 2016年1月29日星期五，Zhihong Luo <zhluo@umich.edu> 写道： > >> Hi Marcus, >> >> Thank you for the information regarding RFNoC. >> >> I am referring to the Block Memory Generator of the Xilinx, which should >> apply to Kintex 7. The thing I want to do is on TX side, I want it to >> periodically send data from the sample data I put in the ram in advance. On >> RX side I want the RAM to serve like a buffer, since I only accept signal >> periodically. I can first put the captured data in the ram first, then send >> it back to PC in a rather slow rate. >> >> Moreover, can we use the usrp sink to receive signal periodically? >> >> Thanks. >> Zhihong Luo >> >> 2016年1月29日星期五，Marcus Müller <usrp-users@lists.ettus.com> 写道： >> >>> This very much sounds like you should actually be using RF Network On >>> Chip, which has the functionality of offering you a clear API within which >>> you can implement your functionality[1][2]. >>> >>> However, "Block RAM" is not a type of IP, but a piece of in-silicon RAM >>> hardware; or are you specifically referring to Xilinx's BRAM IP core, which >>> (as far as I can tell) doesn't apply to the Kintex7 in the X3x0? >>> So: what is it that you want to do with the RAM? >>> >>> Best regards, >>> Marcus >>> >>> [1] https://github.com/EttusResearch/uhd/wiki/RFNoC:--Specification >>> [2] http://www.ettus.com/blog/2015/06/rfnoc-for-high-performance-sdr >>> >>> On 01/29/2016 03:48 AM, Zhihong Luo via USRP-users wrote: >>> >>> Dear all, >>> >>> If I want to insert an IP core into the fpga, like a block ram, what is >>> the right way of doing it? >>> >>> Should I create a folder under /usrp3/top/x300/ip, with .xci file and >>> Makefile.inc in it, then just instantiate it in the source code. Can it >>> work? >>> >>> Thanks, >>> Zhihong >>> >>> >>> _______________________________________________ >>> USRP-users mailing listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >>> >

Hi Zhihong, I'm currently at the fosdem beer event, so it's kind I'd hard to generally agree to that life's pretty complicated ;) In fact, if you use gr-ettus, you can directly connect the block in the FPGA to a GNU radio block. Using it purely with UHD in c++ isn't much different from just getting a normal RX steamer for old-school UHD. Best regards, Marcus Am 29. Januar 2016 20:23:17 MEZ, schrieb Zhihong Luo <zhluo@umich.edu>: >Hi Marcus, > >The RFNoC seems pretty complicated to me since I need to build a new >path >between host and FPGA. And as you said, controlling the radio frontend >may >be a problem. > >Can I modify the fpga (run_rx), so that fpga transmits to usrp source >when >it is not sampling? If so, I think putting sampling data in the RAM >then >sends it back while the usrp is not sampling may be easier. > >Thanks, >Zhihong > >On Fri, Jan 29, 2016 at 11:50 PM, Marcus Müller ><marcus.mueller@ettus.com> >wrote: > >> I'd say the easiest way to do that would be to continously receive >samples >> on the PC and just drop them when you don't need them. >> I don't know how much buffering you need, but: if you use one of the >the >> FPGA images that don't use the external RAM, you can "just" use a >memory >> controller interface, wrap it in an RFNoC block and implement that as >> sample source. The most interesting part here will be how you control >the >> Radio frontend -- that's classically done from the host. >> >> Best regards, >> Marcus >> >> >> On 01/29/2016 03:29 PM, Zhihong Luo wrote: >> >> Sorry, typo, it should be usrp source. >> >> 2016年1月29日星期五，Zhihong Luo <zhluo@umich.edu> 写道： >> >>> Hi Marcus, >>> >>> Thank you for the information regarding RFNoC. >>> >>> I am referring to the Block Memory Generator of the Xilinx, which >should >>> apply to Kintex 7. The thing I want to do is on TX side, I want it >to >>> periodically send data from the sample data I put in the ram in >advance. On >>> RX side I want the RAM to serve like a buffer, since I only accept >signal >>> periodically. I can first put the captured data in the ram first, >then send >>> it back to PC in a rather slow rate. >>> >>> Moreover, can we use the usrp sink to receive signal periodically? >>> >>> Thanks. >>> Zhihong Luo >>> >>> 2016年1月29日星期五，Marcus Müller <usrp-users@lists.ettus.com> 写道： >>> >>>> This very much sounds like you should actually be using RF Network >On >>>> Chip, which has the functionality of offering you a clear API >within which >>>> you can implement your functionality[1][2]. >>>> >>>> However, "Block RAM" is not a type of IP, but a piece of in-silicon >RAM >>>> hardware; or are you specifically referring to Xilinx's BRAM IP >core, which >>>> (as far as I can tell) doesn't apply to the Kintex7 in the X3x0? >>>> So: what is it that you want to do with the RAM? >>>> >>>> Best regards, >>>> Marcus >>>> >>>> [1] https://github.com/EttusResearch/uhd/wiki/RFNoC:--Specification >>>> [2] >http://www.ettus.com/blog/2015/06/rfnoc-for-high-performance-sdr >>>> >>>> On 01/29/2016 03:48 AM, Zhihong Luo via USRP-users wrote: >>>> >>>> Dear all, >>>> >>>> If I want to insert an IP core into the fpga, like a block ram, >what is >>>> the right way of doing it? >>>> >>>> Should I create a folder under /usrp3/top/x300/ip, with .xci file >and >>>> Makefile.inc in it, then just instantiate it in the source code. >Can it >>>> work? >>>> >>>> Thanks, >>>> Zhihong >>>> >>>> >>>> _______________________________________________ >>>> USRP-users mailing >listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>> >>>> >>>> >> -- Sent from my Android device with K-9 Mail. Please excuse my brevity.