On Sun, 30 Sep 2018 19:05:16 +0200
Gerhard Hoffmann dk4xp@arcor.de wrote:

You are right, one can do it simpler, in a single chip:

Take a uC (STM32F030 comes to mind), use its PLL, VCO and clock output
to do the heavy lifting. No external components (beside a few capacitors)
required.

As the CPU itself and all the peripherals are not used, one can do
other shenanigans with them, like playing the imperial march on
a floppy drive.

			Attila Kinali

--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

There's this clock chip that might do it all-in-one. it has a built-in
PLL and several internal dividers for generating clock signals at a
wide range of frequencies. Adafruit has a breakout board for it.
Unfortunately, some people are calling it a DDS even though it's not:
https://www.mouser.com/new/Silicon-Laboratories/silabssi5351/

How about (my original thought, but the above chip may be perfect for
the job) two doublers to generate 40MHz to drive a DDS set to generate
16MHz? This won't EXACTLY be perfect cycle count as 16/40 (or 2/5)
can't be exactly represented in binary, but I calculate that a 32 bit
approximation would lose 1 cycle about every couple of minutes. The
good part is you can calculate exactly how many cycles off you'll be
based on how long it's been running.
On Sat, Sep 29, 2018 at 11:58 PM Tom Van Baak tvb@leapsecond.com wrote:

Hi

If (as originally specified) noise and jitter are not a big deal - there are a lot
of chips out there like the ICS570. They are designed to do weird ratio frequency
conversions so 10 to 12 or 10 to 16 are trivial for them. The Clockblock board was
one way to get it all put together.

Bob

A low phase noise method is to use a dual conjugate regenerative divider with 6MHz and 16Mhz bandpass filters in the feedback loop to produce 16Mhz output.

For 12MHz output use 2MHz and 12MHz bandpass filters in the feedback loop.

Bruce

Hi,

There is clearly enough clock chips today that would fit the bill and
probably provide good enough jitter for you to operate it safely.
Look at products like this:
https://www.silabs.com/products/timing/clocks/general-purpose-clock-generators

There is more of them as you look around.

Then, also consider classic mixer-approach, which may be workable or not
for you:

Square the 10 MHz, feed into a tuned tank for 30 MHz, amplify and
square, divide by 5, mix produced 6 MHz with 10 MHz and amplify into a
tuned tank at 16 MHz, buffer and square as needed for output.

However, for the application at hand I would look at the modern clock
generator chips that has come a long way. Their relatively low noise is
due to their GHz CMOS oscillators and relatively quiet dividers. The
setup gives a relatively good flexibility. Fractional divisors has come
a long way to solve more problems. You get more than the real-estate of
one of the surface mounted DBM mixers would provide you. It's when you
want to go to very low noise that you would consider another approach.

Then again, I would enjoy the challenge of the mixer approach. So choose
method based on what is most rewarding, but for simplicity the clock
chips seems like a good go, so there it is more about locating a cheap
board with the right chip on it.

Cheers,
Magnus

On 9/30/18 5:57 AM, Tom Van Baak wrote:

Bruce-

Does such a dual conjugate regen divider use a single mixer with the BPFs in parallel?  Or are there multiple loops?  I'm trying to visualize the topology.

I've built a few divide-by-2 regen dividers (both worked very well) but nothing else.

-Brian

Hi Brian,

The typical ones have two amplifier chains in parallel and one mixer.
You take the output from the amplifier branch of your liking.

The hard part is to tune them to run in synchronous mode and ensure they
stay there, or else there is a beat pattern causing excessive jitter
over that of the synchronous mode.

Cheers,
Magnus

On 10/3/18 1:54 PM, Brian, WA1ZMS wrote:

Brian
There are 2 parallel feedback paths one tuned to 6MHz and the other tuned to 16MHz.
They can either share the same amp or use separate amplifiers. There's a NIST paper on using them to divide by factors other than 2 (e.g. 3, 5 etc).
https://tf.nist.gov/general/pdf/1890.pdf

Bruce

I just wish the tapr would not discontinue things so fast it seems once you
see it mentioned it's discontinued

On Sun, Sep 30, 2018, 1:08 PM Bob kb8tq kb8tq@n1k.org wrote: