16 MHz VCO divided by 16 to 1 MHz; 10 MHz divided by 10; Phase detector and
loop filter to control the 16 MHz VCO.

Regards,
Tom

----- Original Message -----
From: "Tom Van Baak" tvb@LeapSecond.com
To: "Discussion of precise time and frequency measurement"
time-nuts@lists.febo.com
Sent: Saturday, September 29, 2018 11:57 PM
Subject: [time-nuts] 10 MHz -> 16 MHz

How about an ICS525 or ICS527. IDT’s calculator allows a 0 ppm frequency error. You would need a sine-square converter for input.

People have only as much liberty as they have the intelligence to want and the courage to take.

Emma Goldman

Full wave rectify the sinewave input, extract the 8th Harmonic with a passive filter.
Drive the input of a divide by 5 circuit via a suitable impedance converter network.
Could even use a CMOS 74XX74 flipflop plus a few passive components as the divider.

Bruce

Simple 100 kHz ref frequency PLL  (like old cmos series) with 16 MHz VCXO (
very simple 16MHz xtal with varicap arrangement).
All parts in the ordinary spare generic stuff drawer......

Il domenica 30 settembre 2018, Bruce Griffiths bruce.griffiths@xtra.co.nz
ha scritto:

On Sun, Sep 30, 2018 at 5:58 AM Tom Van Baak tvb@leapsecond.com wrote:

I would square the sine (like HP single BJT or double BJT squarers),
divide by 5 with any 74XX290 or xx390, then multiply by two three
times using 74XX86 XORs with one input delayed by two inverters. You
would need to play with the last inverters delay if your
microcontroller needs a symmetric clock

Frank

Tom,

Divide the 10 MHz down to 2 MHz in the usual way, then multiply by 8
with a cascade of three analog freq doublers separated by fairly narrow
bandpass filters.  Caveats:  Would need four filters total along the path
to get rid of unwanted frequency components, gain distributed along
the path to keep the signal level high enough to satisfy the doublers,
and might suffer excessive phase drift due to temperature changes of
the filters (and probably to a lesser extent) the doublers themselves.
You didn't mention phase stability requirements...

Freq doublers based on mixers or on full-wave rectification have the
pleasant property of having most of their output power in the proper
harmonic order, but require sinusoidal drives to work.  An unfiltered
digital drive signal won't suffice here.

Dana

On Sat, Sep 29, 2018 at 10:58 PM Tom Van Baak tvb@leapsecond.com wrote:

On 09/30/2018 05:57 AM, Tom Van Baak wrote:

When I have needed this, it has been for microcontrollers. I have let
the microcontroller do the locking, with 10MHz applied directly to an
input pin:

I run a reasonably fast* interrupt. Once inside the interrupt, I read
the current timer value, and read the port 8 times into registers.

This gives me 8 samples spaced 45 degrees apart on the 10MHz input,
which are then converted to a 8-bit field.

That 8-bit value is then used in a lookup table, which outputs a phase
value. This is compensated by what was read from the timer (how late we
got into the interrupt).

The phase error is then accumulated, and drives a PWM DAC, connected to
a varactor on the crystal.

It adds 3 external components in total, and for an annoying case like
8/5, it may well wobble 90 degrees.

It started with this Christmas-vacation experiment I never really finished:

https://n1.taur.dk/permanent/synth_v2.pdf

/Kasper Pedersen

*) oscillator_frequency * max_xtal_deviation * 4, typically 16kHz or so.

The clockblock could do that, or probably any of the newer synth chips.  Phase noise and jitter are lousy of course.

On Sep 29, 2018, 11:58 PM, at 11:58 PM, Tom Van Baak tvb@leapsecond.com wrote: