Re: [time-nuts] ANFSCD - Synchronizing time in home video recorders
On Thu, Feb 2, 2012 at 12:21 PM, Tom Van Baak tvb@leapsecond.com wrote:
I'm curious how a 10 MHz-driven high-end DDS would generate
32 kHz with the lowest possible jitter?
I wonder if your 32K diver could be improved if it used interpolation.
In other words use an analog output. So at each cycle you decide
what value to put out, either one or zero or some voltage between.
The next question is why use a PIC divider? Why not a DDS? For
low-end DDS the cost is not much different. Maybe $1 vs. $10 or about
that. (don't say "10X" say "$9 more")
The DDS does about the same thing is a PIC except that at each cycle
it picks an entry from a sine wave table. I don't know if they
interpolate or just use the nearest value. Your algorithm in the
PIC, I think is the same as that but you use nearest value in your
"square wave look up table". Try interpolating. and filtering. This
can move to zero crossing to someplace unrelated to the 10MHz
reference
Chris Albertson
Redondo Beach, California
Now I'm thinking that starting with a first run of 8 cycles at 500nS + 2
cycles at 400nS to be repeated for 10 times and then inserting 2 cycles of
400nS, a first approximation of my 2.048MHz can be done. Maybe with a
deltaF/F of 10 at -4 for tau 1 second but it can be done. In the very long
run the count will be correct and the accuracy gets better tau after tau.
Of course there is the source oscillator's limit.
On Thu, Feb 2, 2012 at 9:21 PM, Tom Van Baak tvb@leapsecond.com wrote:
Hi Roberto:
By changing the timer count dynamically it's possible to lower the jitter
to one timer count. See:
http://www.prc68.com/I/PClock.shtml#BA
Have Fun,
Brooke Clarke
Hi Brooke,
You're a fellow PIC guy; let me explain.
Correct, that method works with a modest interrupt rate to count
integer seconds without long-term rounding error; but to generate
a total of 32,768 as-consistent-as-possible pulses per second
is quite different.
It's possible to use Bresenham with two integers 10,000,000 and
32,768 but I found no way to perform all the 24-bit calculations
on an 8-bit PIC quick enough. Removing the GCD often helps
but in this case the accumulator remains 3-bytes wide.
To generate 32 kHz you have to toggle a pin and calculate if
the next toggle must be 38 or 39 instructions in the future; all
the math must occur within 37 instructions. That's why I came
up with the binary leap year kind of algorithm; it's as close to
math-less as you can get.
By comparison, all the decimal dividers (1 Hz, 10 Hz, etc.) that
you and I do are trivial because of the common factors with the
10 MHz clock. It's just that 32,768 has no factors of 5. Read the
comments in the file 10m32k.c for more details.
I'm curious how a 10 MHz-driven high-end DDS would generate
32 kHz with the lowest possible jitter?
/tvb
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to
https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Hi Tom:
I like the leap year idea. Does this fit into one of the 8-pin PICs?
Have Fun,
Brooke Clarke
http://www.PRC68.com
http://www.end2partygovernment.com/Brooke4Congress.html
Tom Van Baak wrote:
Hi Roberto:
By changing the timer count dynamically it's possible to lower the jitter to one timer count. See:
http://www.prc68.com/I/PClock.shtml#BA
Have Fun,
Brooke Clarke
Hi Brooke,
You're a fellow PIC guy; let me explain.
Correct, that method works with a modest interrupt rate to count
integer seconds without long-term rounding error; but to generate
a total of 32,768 as-consistent-as-possible pulses per second
is quite different.
It's possible to use Bresenham with two integers 10,000,000 and
32,768 but I found no way to perform all the 24-bit calculations
on an 8-bit PIC quick enough. Removing the GCD often helps
but in this case the accumulator remains 3-bytes wide.
To generate 32 kHz you have to toggle a pin and calculate if
the next toggle must be 38 or 39 instructions in the future; all
the math must occur within 37 instructions. That's why I came
up with the binary leap year kind of algorithm; it's as close to
math-less as you can get.
By comparison, all the decimal dividers (1 Hz, 10 Hz, etc.) that
you and I do are trivial because of the common factors with the
10 MHz clock. It's just that 32,768 has no factors of 5. Read the
comments in the file 10m32k.c for more details.
I'm curious how a 10 MHz-driven high-end DDS would generate
32 kHz with the lowest possible jitter?
/tvb
time-nuts mailing list -- time-nuts@febo.com
To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
On Thu, Feb 2, 2012 at 12:21, Tom Van Baak tvb@leapsecond.com wrote:
It's possible to use Bresenham with two integers 10,000,000 and
32,768 but I found no way to perform all the 24-bit calculations
on an 8-bit PIC quick enough. Removing the GCD often helps
but in this case the accumulator remains 3-bytes wide.
In this particular case, the divisor your want is 2^15 / 10^7. You
can remove a common factor of 2^7, giving 2^8 / 5^7, or 256 / 78125.
If you only want a square wave output, you should be able to do this
with a 17-bit binary counter and some logic. In concept, it looks
something like:
- initialize register to 0
- every input clock, add 256 to the register
- when the register is greater than or equal to 78125, set overflow
bit and subtract 78125 from the register.
In practice, you'd probably set the register to 78125 and count down
to zero, using the "borrow" output from the subtract of 256 as
overflow. Then you don't need to compare the register to 78125.
Essentially, you've built a special-purpose DDS whose frequency
resolution is 128 Hz , and the output frequency you want is exactly
256*128 Hz. The average frequency is exact, and the output waveform
repeats every 1/128 sec.
I'm curious how a 10 MHz-driven high-end DDS would generate
32 kHz with the lowest possible jitter?
You should be able to use a AD9913 to do the same 256/78125 division
described above, with exact output frequency, and sine wave output to
boot. If I've understood the datasheet correctly, you would program
the main DDS frequency tuning word to 14073748, which gets you as
close to 32768 Hz as possible without exceeding it. Using variable
modulus mode, you program the FTW and modulus of the secondary DDS to
65276 and 78125.
Every input clock, the main FTW of 14073748 is added to the main
32-bit register. At the same time, 65276 is added to the secondary
register. If the secondary register exceeds 78125 (which will happen
on most clocks with these values), the main register is incremented by
1 and the secondary register has 78125 subtracted. So over the course
of 78125 input clocks (1/128 second), the secondary register has
6527678125 counts total added, which causes it to overflow 65276
times. The main register has 7812514073748 added to it directly,
plus 65276 extra counts from the secondary register overflows. The
sum of those two values is exactly 2^40, meaning the main register
overflows 2^8 times in 78125 clocks.
After 78125 input clocks, both the main and secondary register have
returned to zero, so the sequence repeats exactly every 1/128 second.
In effect, the secondary register is acting as a variable-modulus DDS
that changes the FTW of the primary fixed-modulus DDS by only one
count, just often enough to make the division ratio exact. And
because the primary DDS is still fixed-modulus, you can still use the
top k bits of the accumulator to index into a sine lookup table, and
produce a sine wave output.
Dave