What sort of crystals do you find inside?  My guess is there are two of them,
one at 32KHz used for timekeeping, and one at ?? MHz for the CPU.

I think I've seen comments about making 32 KHz from 10 MHz in a PIC or AVR.

tvb has this web page, but I don't see a 32 KHz option:
http://www.leapsecond.com/pic/picdiv.htm

Anyway, the idea would be to find the 32 KHz crystal inside your DVR and
replace it with 32 KHz derived from your TBolt.  Most of the clock chips have
an internal amplifier connected across 2 pins, often labeled something like
X-out and X-in.  The idea is to put a signal on X-in and ignore X-out.

I'd probably take a look with a scope, and then see if I can make something
with a few resistors to get the right level and a 1-meg to connect that
signal to X-in.

--
These are my opinions, not necessarily my employer's.  I hate spam.

Hal,

Yes, I have a PIC divider that takes 5 or 10 MHz input and
outputs a 32.768 kHz square wave with minimal jitter and
no long-term phase offset. Contact me off-line if interested.

/tvb

Hi Tom,

I'm interested in that divider. Actually, insterested in knowing how it
works, not in the .HEX file.

Breseham's algorith works but has inherent jitter and I've found no other
solutions for situations like that.

I'd live to know how it is done.

Thank you,
Roberto EB4EQA
http://www.rbarrios.com

-----Mensaje original-----
From: Tom Van Baak
Sent: Thursday, February 02, 2012 10:34 AM
To: Discussion of precise time and frequency measurement
Subject: Re: [time-nuts] ANFSCD - Synchronizing time in home video recorders

Hal,

Yes, I have a PIC divider that takes 5 or 10 MHz input and
outputs a 32.768 kHz square wave with minimal jitter and
no long-term phase offset. Contact me off-line if interested.

/tvb

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Hi Roberto,

The motivation for this, I assume most list members know, is to
drive cheap quartz stepper motor clocks with precise 32 kHz
frequency, one derived from an atomic or GPS 10 MHz.

The 10 MHz to 32 kHz PIC divider I wrote uses a sort of binary
"leap year" algorithm to adjust the digital output phase to be as
close as possible to the ideal 32.768 kHz phase on each cycle
and also to have zero long-term error.

I'm not sure how well a multi-level leap year algorithm relates
Breseham's algorithm. I tracked down his 1965 plotter article.
There might be common ground there.

With non-integral ratios like this case, or without external analog
components (e.g., PLL), it seems some level of jitter is always
unavoidable. So the goal was to make it as mathematically small
as possible, and furthermore, to be able to do the math within a
half cycle, which is only 15 microseconds.

I'll send you an early draft of the PIC code; the version that was
most clear before I had to pinch too many cycles and added too
many features. Let me know what you think.

I also simulated the algorithm on a PC and measured the ADEV
and phase noise. That simulation code is file 10m32k.c under:

http://www.leapsecond.com/tools/

/tvb

----- Original Message -----
From: "Roberto Barrios" rbarrioss@msn.com
To: "Tom Van Baak" tvb@leapsecond.com; "Discussion of precise time and frequency measurement" time-nuts@febo.com
Sent: Thursday, February 02, 2012 5:09 AM
Subject: Re: [time-nuts] ANFSCD - Synchronizing time in home video recorders

Amazing... there is always something to learn from TVB. Now I'll try to
derive a 2.048MHz G.703-13 clock from a 10MHz clock. I suspect that the
procedure is similar, even if 2048KHz is not quite a power of 2.

On Thu, Feb 2, 2012 at 4:35 PM, Tom Van Baak tvb@leapsecond.com wrote:

Yes, shortly after having sent out the message I realized that I was, as
usual, too fast. I'm aware that a simple microprocessor can't be used but a
Spartan3 can be involved. Then another problem: the 2.048MHz is about 1/5
of the 10MHz so it is not possible. Sofar the way out is: dividing the
10MHz by 625 and then multiplying by 128 using the DCM in the Spartan3...
but nothing clever in this method. Sorry, not a valid contribution.

On Thu, Feb 2, 2012 at 6:07 PM, Tom Van Baak tvb@leapsecond.com wrote:

Hi Roberto:

By changing the timer count dynamically it's possible to lower the jitter to one timer count.  See:
http://www.prc68.com/I/PClock.shtml#BA

Have Fun,

Brooke Clarke
http://www.PRC68.com
http://www.end2partygovernment.com/Brooke4Congress.html

Roberto Barrios wrote:

Hi Brooke,

You're a fellow PIC guy; let me explain.

Correct, that method works with a modest interrupt rate to count
integer seconds without long-term rounding error; but to generate
a total of 32,768 as-consistent-as-possible pulses per second
is quite different.

It's possible to use Bresenham with two integers 10,000,000 and
32,768 but I found no way to perform all the 24-bit calculations
on an 8-bit PIC quick enough. Removing the GCD often helps
but in this case the accumulator remains 3-bytes wide.

To generate 32 kHz you have to toggle a pin and calculate if
the next toggle must be 38 or 39 instructions in the future; all
the math must occur within 37 instructions. That's why I came
up with the binary leap year kind of algorithm; it's as close to
math-less as you can get.

By comparison, all the decimal dividers (1 Hz, 10 Hz, etc.) that
you and I do are trivial because of the common factors with the
10 MHz clock. It's just that 32,768 has no factors of 5. Read the
comments in the file 10m32k.c for more details.

I'm curious how a 10 MHz-driven high-end DDS would generate
32 kHz with the lowest possible jitter?

/tvb

On Thu, Feb 2, 2012 at 12:21 PM, Tom Van Baak tvb@leapsecond.com wrote:

I wonder if your 32K diver could be improved if it used interpolation.
In other words use an analog output.  So at each cycle you decide
what value to put out, either one or zero or some voltage between.

The next question is why use a PIC divider?  Why not a DDS?  For
low-end DDS the cost is not much different.  Maybe $1 vs. $10 or about
that. (don't say "10X" say "$9 more")

The DDS does about the same thing is a PIC except that at each cycle
it picks an entry from a sine wave table.  I don't know if they
interpolate or just use the nearest value.  Your algorithm in the
PIC, I think is the same as that but you use nearest value in your
"square wave look up table".  Try interpolating. and filtering.  This
can move to zero crossing to someplace unrelated to the 10MHz
reference

Chris Albertson
Redondo Beach, California

Now I'm thinking that starting with a first run of 8 cycles at 500nS + 2
cycles at 400nS to be repeated for 10 times and then inserting 2 cycles of
400nS, a first approximation of my 2.048MHz can be done. Maybe with a
deltaF/F of 10 at -4 for tau 1 second but it can be done. In the very long
run the count will be correct and the accuracy gets better tau after tau.
Of course there is the source oscillator's limit.

On Thu, Feb 2, 2012 at 9:21 PM, Tom Van Baak tvb@leapsecond.com wrote:

Hi Tom:

I like the leap year idea.  Does this fit into one of the 8-pin PICs?

Have Fun,

Brooke Clarke
http://www.PRC68.com
http://www.end2partygovernment.com/Brooke4Congress.html

Tom Van Baak wrote:

On Thu, Feb 2, 2012 at 12:21, Tom Van Baak tvb@leapsecond.com wrote:

In this particular case, the divisor your want is 2^15 / 10^7.  You
can remove a common factor of 2^7, giving 2^8 / 5^7, or 256 / 78125.

If you only want a square wave output, you should be able to do this
with a 17-bit binary counter and some logic.  In concept, it looks
something like:

• initialize register to 0
• every input clock, add 256 to the register
• when the register is greater than or equal to 78125, set overflow
  bit and subtract 78125 from the register.

In practice, you'd probably set the register to 78125 and count down
to zero, using the "borrow" output from the subtract of 256 as
overflow.  Then you don't need to compare the register to 78125.

Essentially, you've built a special-purpose DDS whose frequency
resolution is 128 Hz , and the output frequency you want is exactly
256*128 Hz.  The average frequency is exact, and the output waveform
repeats every 1/128 sec.

You should be able to use a AD9913 to do the same 256/78125 division
described above, with exact output frequency, and sine wave output to
boot.  If I've understood the datasheet correctly, you would program
the main DDS frequency tuning word to 14073748, which gets you as
close to 32768 Hz as possible without exceeding it.  Using variable
modulus mode, you program the FTW and modulus of the secondary DDS to
65276 and 78125.

Every input clock, the main FTW of 14073748 is added to the main
32-bit register.  At the same time, 65276 is added to the secondary
register.  If the secondary register exceeds 78125 (which will happen
on most clocks with these values), the main register is incremented by
1 and the secondary register has 78125 subtracted.  So over the course
of 78125 input clocks (1/128 second), the secondary register has
6527678125 counts total added, which causes it to overflow 65276
times.  The main register has 7812514073748 added to it directly,
plus 65276 extra counts from the secondary register overflows.  The
sum of those two values is exactly 2^40, meaning the main register
overflows 2^8 times in 78125 clocks.

After 78125 input clocks, both the main and secondary register have
returned to zero, so the sequence repeats exactly every 1/128 second.
In effect, the secondary register is acting as a variable-modulus DDS
that changes the FTW of the primary fixed-modulus DDS by only one
count, just often enough to make the division ratio exact.  And
because the primary DDS is still fixed-modulus, you can still use the
top k bits of the accumulator to index into a sine lookup table, and
produce a sine wave output.

 Dave