I have used the switched capacitor type, with direct control over the
switching caps .

We were able to high speed dither the switch settings to get 1/2 and 1/4
and 1/8 steps of the minimum capacitor switch step. This way, we got
high control resolution.

BUT- this only works for requirements that are tolerant of the switching
spurs, phase mod etc.

The medium term frequency stability was important - over seconds -  not
very short term of milli seconds.

If I need very low noise I use a varactor (capacitance) or YIG style
control , analog LPF and single bit sigma delta converter in the FPGA 
(free in FPGA fabric) , and a then fractional dither to get my sub-bit 
resolution.

-glen

On 19/02/2022 11:24 am, Magnus Danielson via time-nuts wrote:

A while back I purchased a low cost TCXO which I then used as the reference
for a synthesizer generating 10GHz.  Listening to the output on an SSB
radio, the tone was hopping in a random fashion over four frequencies,
spaced a few tens of Hz apart.  This was surreal!  I had, at that time,
been building Multifrequency Shift Keyed data sources ( for WSJT modes) by
programming synths directly, but this wasn't the case here.  Yet the
hopping tones sounded just like the modulation I would eventually be adding.
Double checking, then again, then again. that I hadn't inadvertently
programmed the synth controller PIC with the wrong code, had to come to the
conclusion it was the TCXO using a PRN sequence to effect digital
temperature/frequency compensation.    At its 10MHz fundamental, each hop
would have been a few tens of millihertz.

But it was very weird at first, hearing what sounded like a familiar
modulation on a synth that wasn't programmed to generate it.  There were
four tones hopping in a (presumably pseudo) random manner, and the WSJT
mode I was going to use, JT4, had... four tones that hop around.

Andy
www.g4jnt.com

On Fri, 18 Feb 2022 at 10:19, Erik Kaashoek erik@kaashoek.com wrote:

Hi

Sounds like you might want to try a different TCXO. Or even
try an OCXO. Even with a good TCXO, 1x10^-9 accuracy is
a stretch. I’m assuming we’re talking frequency accuracy so
the usual “one sigma” time accuracy not the overriding number.

GPS module “output jitter” forces you to a fairly long filter time
constant to achieve better than that. Hitting the usual “>99% of the
samples at a 10 second gate" sort of frequency accuracy spec
drives you to numbers out past 100 seconds.

The TCXO (even a good one) in a fairly normal ambient gets hit
by all sorts of small thermal changes. You can try this or try that,
in a real world portable setting … there is “thermal rumble”. The
TCXO will struggle to stay on frequency as it sees that rumble.

Bob

Erik,

So, your pick of VC-TCXO is one that obviously seems to use the
fractional synthesis to both set the output frequency as well as
compensate for temperature. The modulations you have will be intrinsic
to the pick.

As you lock your VC-TCXO to a GPS, the average frequency will be locked
to the GPS, but the variations you have from steering will remain. The
control theory of a PLL lock says that you will low-pass filter the
signal on the reference and high-pass filter the noise of the
oscillator. The cut-over frequency is the same, the bandwidth of the
PLL. The actual responses will also be coloured by the damping factor,
which should be kept high to avoid bumps. A rule of thumb is to ensure
you keep the damping factor at least 3 or higher. Now, that remains of
you shifts will be the spikes of the shift, and you really do not get
rid of them unless you have a second cleanup PLL that can low-pass
filter out them. This assumes naturally that you have a quiet oscillator
in the clean-up, and the lesson being, you should be using that
oscillator instead most of the times. The special case is when you have
a somewhat dirty but stable oscillator so you can do hold-over in
unlocked conditions, and then use a clean but less table oscillator as
clean-up. However, many times you can just get a clean oscillator and
avoid the issue, resulting in a simpler and cleaner design, which may be
beneficial as you get a more compact and less power-hungry setup.

These disturbances can eat your precision if you do frequency counters
or spectrum analysis. Actual frequency precision is not the only
measure, but phase-noise and ADEV stability (as perscribed in IEEE Std
1139).

It sounds like you have yourself a fine little oscillator there, but it
may be unfit for your application. I've seen that so many times. Being
"in spec" in terms of the datasheet does not necessarily makes it "in
spec" for the application. At best datasheets help you coarse-select
candidates, but then they need to be tested that their basic behaviour
is compliant with all the performance needs of the actual application.
Learning what is relevant and not for an application is a learning
experience, and one set of experience may or may not be relevant for
another users needs. If one only use high quality oscillators, the types
of tricks being used in high volume low cost oscillators to provide some
set of performance can cause surprises. Either one learn to live with
them, or find ways to compensate them.

For instance, the low frequency PWM pattern you have on frequency you
measured creates a phase-deviation that looks like a triangular wave
shape. It will sweep from equal-slope triangular over to sawtooth shape.
The acceleration spikes as frequency shift at th ends will stress a
follow-up loop. The time-deviation of the oscillator will limit what you
can do with it for other measures. The time-deviation can be
characterized in the standard MTIE curve that measure max max-to-min
time-deviation. This is important in telecom applications, as it
translates to buffer-size. It will also be important in time-interval
measurements.

OK, do let's calculate the peak-to-peak of the phase. You measured a
step difference of about 20 mHz and a period of 107 s. Now let's just
assume that we set it up to synthesize 10 mHz, that is just inbetween
the two steps. This means half the time it would be set to the lower
frequency and the other half to the high frequency, and it now becomes
trivial to see that the frequency synthesis goal is reached. However, it
means that it spends about 50 s at +10 mHz and then 50 s at -10 mHz of
that average. This produces a phase-ramp going -0.5 s and then +0.5 s,
since 0.01 * 50 = 0.5 s. The peak-to-peak time is thus half a second.
That is really bad. This is the problem with long PWM on frequency.

For one design I did, I built a reversed PWM spectrum modulation, which
actually had about the same logic complexity of PWM. It forced the most
significant energy to the highest possible frequency, where it becomes
trivial to filter. For that system I had both an analog filter and the
filtering of the VC-OCXO. The side-consequence is also that the ramp of
phase error keeps being moved up and down at high rate and only ower
components would be seen, but much damped. Any remaining phase issue is
then controlled by the loop as it is a phase-lock and those errors is at
low enough frequency to be suprpessed by the high-pass function of the
PLL. Also, for my case, the issue was small since it was a way to cram
out 19 bits out of a 16 bit DAC, so the amplitude was scalled down by
1/65536 of full-scale and then by the sensitivity of the EFC input.

We have to do these ugly tricks in real life engineering, but the trick
is learning to cheat where it doesn't hurt too much. Telling about these
things I hope is illustrative enough to be a good reading.

Cheers,
Magnus

On 2022-02-19 09:24, Erik Kaashoek wrote:

Andy, do you have the PIC and the synthesiser chip data control lines
well buffered/isolated (nice big resistors etc on the data lines ?)

Any sort of current you inject into the synth chip will find its way
onto the output....

On 19/02/2022 7:55 pm, Andy Talbot wrote:

Erik,

What you describe is a classic problem. Especially oven controlled
oscillators will have GND and VCC issues.

I recommend you to look att both frequency and phase deviation plots.
Systematics like these is mangled up in a ADEV plot.

Regardless of what isuse you really had, I hope you learned a bunch from
all the different comments. A failure you learn from is not a failure,
it's an experience. A failure you do not learn from, is the real failure.

Keep going!

Cheers,
Magnus

On 2022-02-19 21:18, Erik Kaashoek wrote:

At that time the synth was set to one frequency and the code went into
sleep , so any buffering resistors etc would have served no purpose.
The TCXO really was hopping over four frequencies in a PN way at intervals
of a little under one second per hop.

Andy
www.g4jnt.com

On Sat, 19 Feb 2022 at 20:46, glen english LIST glenlist@cortexrf.com.au
wrote:

On Freitag, 18. Februar 2022 22:52:27 CET Attila Kinali wrote:

I can think of better reasons.  :-)

This type of tuning requires ridiculously low power in comparison to anything
else you'd be able to come up with, which is of utmost importance if you are
talking about RTC.  For TCXO (or just XO) the excellent linearity of MOM or
MIM capacitors at high signal amplitude would probably rank high on the
requirement sheet.

No, any CMOS process provides you with a MOS varactor (at least two different
ones depending on how deep into the woods you will go).  It has a limited
tuning range and some biasing requirements that can be a headache (also
significant temperature dependence).  These are also the ones with the highest
capacitance per area in a modern CMOS process, so the cheapest option overall.

Yes, ideally you'd want a hyperabrupt junction for highest tuning range.  In a
CMOS integrated process you just take whatever you already have that gets you
closest to that ideal, maybe add one more implant if the varactor diode is
something someone actually pays for.  It's usually not quite good enough for
GHz RF applications if you care about Q, but it'd totally work at 10MHz.

Regards,
Achim.

+<[Q+ Matrix-12 WAVE#46+305 Neuron microQkb Andromeda XTk Blofeld]>+

SD adaptation for Waldorf rackAttack V1.04R1:
http://Synth.Stromeko.net/Downloads.html#WaldorfSDada