Oops, not sure how this didn’t make it to USRP list. >Ettus Research is very excited to announce the release of RFNoC! […] This is very cool. I’ve been looking forward to working with this development. > Mixing and matching host-based and FPGA-based processing is transparent to the user, and that processing can scale across multiple FPGAs and devices across a network Does this imply that I could run a GNU Radio application on a Zedboard, for instance, with the following data flows: (1) GR on Zynq ARM --> Zynq FPGA --> GR on Zynq ARM --> B2x0 RF/radio (2) GR on Zynq ARM --> Zynq FPGA --> GR on Zynq ARM --> X3x0 FPGA --> X3x0 RF/radio I think (1) is similar or identical to Jonathon Pendlum’s FPGA filter demo. What I’m more curious about is how easy it is to build a single GR flowgraph that mixes GR processing with FPGAs that live either in Zynq or connected 3x0 series devices. It sounds like this kind of support is an explicit goal of RFNoC.

On Dec 4, 2014, at 2:03 PM, "Nowlan, Sean via USRP-users" <usrp-users@lists.ettus.com> wrote: > Oops, not sure how this didn’t make it to USRP list. > > That was weird, I got your original via USRP-users even though it wasn't on the To: list…bcc? > >Ettus Research is very excited to announce the release of RFNoC! > > […] > > This is very cool. I’ve been looking forward to working with this development. > > > Mixing and matching host-based and FPGA-based processing is transparent to the user, and that processing can scale across multiple FPGAs and devices across a network > > Does this imply that I could run a GNU Radio application on a Zedboard, for instance, with the following data flows: > > (1) GR on Zynq ARM --> Zynq FPGA --> GR on Zynq ARM --> B2x0 RF/radio > (2) GR on Zynq ARM --> Zynq FPGA --> GR on Zynq ARM --> X3x0 FPGA --> X3x0 RF/radio > > I think (1) is similar or identical to Jonathon Pendlum’s FPGA filter demo. What I’m more curious about is how easy it is to build a single GR flowgraph that mixes GR processing with FPGAs that live either in Zynq or connected 3x0 series devices. It sounds like this kind of support is an explicit goal of RFNoC. So if you are asking can RFNoC create arbitrary paths in a flow graph where data flow passes Host-based-GR -> FPGA -> Host-based-GR, then yes, that was one of the original architecture goals. > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com