Empathy List Archives

GH

Gerhard Hoffmann

Tue, Mar 24, 2020 10:05 PM

Am 24.03.20 um 20:06 schrieb Attila Kinali:

If you want an SDR like system to play with, try the

Red Pitaya?

You get 2 ADC channels 125MHz/14Bit or 128.x MHz/16 Bit,
2 DAC channels, 2 ARM CPUs, Network etc and it boots Linux when
you plug in an USB power supply. It has existing apps such as scope,
vector network analyzer, Bode plotter, ham radio etc - and the
software as well as the web server that presents the results to
your browser is open.
It's fun to watch tuning S21 of a filter in Firefox. :-)

With 2 boards one could do the whole cross correlation thing,
with at least the 2 ADC pairs completely isolated.
< https://www.redpitaya.com/Catalog >
Prices are reasonable.

While I'm at it:

Is there a done solution to expand a Timepod to
~ 100 MHz, narrow-bandish is OK. I'm willing to solder,
but I'm not ready for yet another development project.
Not now.

When I've flushed my project pipeline, I might consider
something serious with JESD-204B ADCs and such.
That would require a larger FPGA with GTX transceivers
and maybe a Beaglebone as a controller.

cheers, Gerhard

<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

Does Zuerich have a good part? That's news! No one threw
chocolate at me. Driving in the inner city of Berlin in
the rushhour is the pure relaxation in comparison.
Never ever again! =8-( )

Am 24.03.20 um 20:06 schrieb Attila Kinali: > > If you want an SDR like system to play with, try the Red Pitaya? You get 2 ADC channels 125MHz/14Bit or 128.x MHz/16 Bit, 2 DAC channels, 2 ARM CPUs, Network etc and it boots Linux when you plug in an USB power supply. It has existing apps such as scope, vector network analyzer, Bode plotter, ham radio etc - and the software as well as the web server that presents the results to your browser is open. It's fun to watch tuning S21 of a filter in Firefox. :-) With 2 boards one could do the whole cross correlation thing, with at least the 2 ADC pairs completely isolated. < https://www.redpitaya.com/Catalog > Prices are reasonable. While I'm at it: Is there a _done_ solution to expand a Timepod to ~ 100 MHz, narrow-bandish is OK. I'm willing to solder, but I'm not ready for yet another development project. Not now. When I've flushed my project pipeline, I might consider something serious with JESD-204B ADCs and such. That would require a larger FPGA with GTX transceivers and maybe a Beaglebone as a controller. cheers, Gerhard <JaberWorky> The bad part of Zurich is where the degenerates throw DARK chocolate at you. Does Zuerich have a good part? That's news! No one threw chocolate at me. Driving in the inner city of Berlin in the rushhour is the pure relaxation in comparison. Never ever again! =8-( )

J

jimlux

Tue, Mar 24, 2020 11:31 PM

On 3/24/20 2:17 PM, John Miles wrote:

It would be interesting to know what ADC was used and if there's an
SDR-board out there that uses the same ADC.

Uh.. I remember John telling me what ADC it was, but I forgot, sorry.

It uses four AD9265s. The TimePod used four LTC2216s, but the AD9265s
support higher clock rates with less power consumption, and both of those
attributes were important this time around.

And they work in space, should one care about that.. They also have nice
low clock input noise.
(i.e. the SNR isn't too degraded from the ideal, compared to some other
fast ADCs).

I am pretty sure I could design something like the PhaseStation as well.
The working principle is easy and can be explained on a napkin in 5

minutes.

But getting it to this remarkable perfomrance? Not without a lot of
trial and error. And even then, I wouldn't be sure.

I don't think there's any way to avoid the trial-and-error part unless you
have the luxury of an unlimited ceiling for both the R&D budget and the
target retail price, and maybe not even then. One reason it took longer
than expected to ship the 53100A was that a lot of lessons that I thought
had been adequately learned on the 5330A/3120A project didn't pay off when
different ADCs were used, and when the carrier and offset frequency
requirements grew by 6x and 10x respectively.

With the TimePod, for example, noise and spur performance weren't strongly
influenced by ADC clock distribution. On PhaseStation, that particular
"unlearned lesson" cost me a respin.

That is a real lesson - It's one that people doing their first low noise
systems get burned by (do NOT run your clock signal from your quiet
oscillator through the FPGA, and yes, that fancy fast clock driver might
actually degrade performance because it has a 1GHz BW and so does the
clock input on the ADC...)

And then, getting the data reliably out of the ADC into the FPGA, and
synchronized across multiple channels. That particular part doesn't
guarantee the startup state of the internal pipeline.

Keeping parts and manufacturing costs under control was also more difficult
than anticipated. Another lesson that wasn't learned soon enough was that a
design with four or five internal PCBs ends up being much more expensive
than one that uses only two, even if the total board area is similar. We
had to increase the price twice to maintain standard T&M industry margins,
and (having just come back from visiting Said and Giovanni at Jackson Labs)
that's about to happen again. The original vision of a four-figure price
tag was unrealistic, and that's definitely a lesson for next time.

is that because of connectors and interfaces?
Or because of "unit test" time and process?

I know that for space stuff, all on one board or in one box is cheaper
than breaking it up, particularly for RF systems. Because if it's
individual widgets, everyone wants individual test data at the widget
level, before you combine them into superwidget assemblies.

-- john, KE5FX
Miles Design LLC / Jackson Labs Technologies, Inc.

time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.

On 3/24/20 2:17 PM, John Miles wrote: >>> It would be interesting to know what ADC was used and if there's an >>> SDR-board out there that uses the same ADC. >> >> Uh.. I remember John telling me what ADC it was, but I forgot, sorry. > > It uses four AD9265s. The TimePod used four LTC2216s, but the AD9265s > support higher clock rates with less power consumption, and both of those > attributes were important this time around. > And they work in space, should one care about that.. They also have nice low clock input noise. (i.e. the SNR isn't too degraded from the ideal, compared to some other fast ADCs). >> I am pretty sure I could design something like the PhaseStation as well. >> The working principle is easy and can be explained on a napkin in 5 > minutes. >> But getting it to this remarkable perfomrance? Not without a lot of >> trial and error. And even then, I wouldn't be sure. > > I don't think there's any way to avoid the trial-and-error part unless you > have the luxury of an unlimited ceiling for both the R&D budget and the > target retail price, and maybe not even then. One reason it took longer > than expected to ship the 53100A was that a lot of lessons that I *thought* > had been adequately learned on the 5330A/3120A project didn't pay off when > different ADCs were used, and when the carrier and offset frequency > requirements grew by 6x and 10x respectively. > > With the TimePod, for example, noise and spur performance weren't strongly > influenced by ADC clock distribution. On PhaseStation, that particular > "unlearned lesson" cost me a respin. That is a real lesson - It's one that people doing their first low noise systems get burned by (do NOT run your clock signal from your quiet oscillator through the FPGA, and yes, that fancy fast clock driver might actually degrade performance because it has a 1GHz BW and so does the clock input on the ADC...) And then, getting the data reliably out of the ADC into the FPGA, and synchronized across multiple channels. That particular part doesn't guarantee the startup state of the internal pipeline. > > Keeping parts and manufacturing costs under control was also more difficult > than anticipated. Another lesson that wasn't learned soon enough was that a > design with four or five internal PCBs ends up being much more expensive > than one that uses only two, even if the total board area is similar. We > had to increase the price twice to maintain standard T&M industry margins, > and (having just come back from visiting Said and Giovanni at Jackson Labs) > that's about to happen again. The original vision of a four-figure price > tag was unrealistic, and that's definitely a lesson for next time. is that because of connectors and interfaces? Or because of "unit test" time and process? I know that for space stuff, all on one board or in one box is cheaper than breaking it up, particularly for RF systems. Because if it's individual widgets, everyone wants individual test data at the widget level, before you combine them into superwidget assemblies. > > -- john, KE5FX > Miles Design LLC / Jackson Labs Technologies, Inc. > > > > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there. >

JM

John Miles

Wed, Mar 25, 2020 12:38 AM

And then, getting the data reliably out of the ADC into the FPGA, and
synchronized across multiple channels. That particular part doesn't
guarantee the startup state of the internal pipeline.

There's a sync pin for use with the clock divider, but AFAIK it does nothing
when the divider isn't used (which it isn't). Fortunately, fixed delay
between channels isn't a big concern, as long as it stays put. With a 1:1
clock, the time from clock in to DCO out is always consistent.

is that because of connectors and interfaces?
Or because of "unit test" time and process?

Mostly the former, as we test the system as a whole. Multiple boards cost
more at the PCB fab and cost more to stuff, and of course the interconnects
are both an expense on the BOM and a liability during assembly. The front
panel and input PCB alone have two dozen SMA jacks, so assembly training and
documentation isn't a trivial matter.

Then there's the additional mounting hardware and assembly steps associated
with multiple boards. And while we test at the system level as noted, the
test script has to do its best to narrow down failures at the subassembly
level, rather than simply reporting go/no-go conditions. Lots of little
things that add up to real costs.

I know that for space stuff, all on one board or in one box is cheaper
than breaking it up, particularly for RF systems. Because if it's
individual widgets, everyone wants individual test data at the widget
level, before you combine them into superwidget assemblies.

Yes, and I'm sure the cost of the interconnects and mounting hardware is
insane in that business!

-- john

> And then, getting the data reliably out of the ADC into the FPGA, and > synchronized across multiple channels. That particular part doesn't > guarantee the startup state of the internal pipeline. There's a sync pin for use with the clock divider, but AFAIK it does nothing when the divider isn't used (which it isn't). Fortunately, fixed delay between channels isn't a big concern, as long as it stays put. With a 1:1 clock, the time from clock in to DCO out is always consistent. > is that because of connectors and interfaces? > Or because of "unit test" time and process? Mostly the former, as we test the system as a whole. Multiple boards cost more at the PCB fab and cost more to stuff, and of course the interconnects are both an expense on the BOM and a liability during assembly. The front panel and input PCB alone have two dozen SMA jacks, so assembly training and documentation isn't a trivial matter. Then there's the additional mounting hardware and assembly steps associated with multiple boards. And while we test at the system level as noted, the test script has to do its best to narrow down failures at the subassembly level, rather than simply reporting go/no-go conditions. Lots of little things that add up to real costs. > I know that for space stuff, all on one board or in one box is cheaper > than breaking it up, particularly for RF systems. Because if it's > individual widgets, everyone wants individual test data at the widget > level, before you combine them into superwidget assemblies. Yes, and I'm sure the cost of the interconnects and mounting hardware is insane in that business! -- john

JM

John Miles

Wed, Mar 25, 2020 1:00 AM

Is there a done solution to expand a Timepod to
~ 100 MHz, narrow-bandish is OK. I'm willing to solder,
but I'm not ready for yet another development project.
Not now.

A pair of double-balanced mixers driven by independent signal generators works well. The mixer RF inputs are driven by a splitter, while the IF outputs go to channels 0 and 2. Add gain/loss as needed.

Independent bandpass filters at each mixer RF port can be helpful, since common-mode noise on the unwanted sideband can cause artifacts. It will usually (but not always) be fairly obvious when you have problems with this.

When I've flushed my project pipeline, I might consider
something serious with JESD-204B ADCs and such.
That would require a larger FPGA with GTX transceivers
and maybe a Beaglebone as a controller.

Some of the newer parts are pretty tempting, but note that the need for wideband acquisition is driven by offset frequency range rather than carrier frequency range. Most noise measurement applications won't need 100 MHz-1 GHz of acquisition bandwidth, unlike the wireless base stations and high-end signal analyzers that the ADC manufacturers are targeting.

-- john

> Is there a _done_ solution to expand a Timepod to > ~ 100 MHz, narrow-bandish is OK. I'm willing to solder, > but I'm not ready for yet another development project. > Not now. A pair of double-balanced mixers driven by independent signal generators works well. The mixer RF inputs are driven by a splitter, while the IF outputs go to channels 0 and 2. Add gain/loss as needed. Independent bandpass filters at each mixer RF port can be helpful, since common-mode noise on the unwanted sideband can cause artifacts. It will usually (but not always) be fairly obvious when you have problems with this. > When I've flushed my project pipeline, I might consider > something serious with JESD-204B ADCs and such. > That would require a larger FPGA with GTX transceivers > and maybe a Beaglebone as a controller. Some of the newer parts are pretty tempting, but note that the need for wideband acquisition is driven by offset frequency range rather than carrier frequency range. Most noise measurement applications won't need 100 MHz-1 GHz of acquisition bandwidth, unlike the wireless base stations and high-end signal analyzers that the ADC manufacturers are targeting. -- john

BK

Bob kb8tq

Wed, Mar 25, 2020 1:00 AM

Hi

On Mar 24, 2020, at 7:31 PM, jimlux jimlux@earthlink.net wrote:

On 3/24/20 2:17 PM, John Miles wrote:

It would be interesting to know what ADC was used and if there's an
SDR-board out there that uses the same ADC.

Uh.. I remember John telling me what ADC it was, but I forgot, sorry.

It uses four AD9265s. The TimePod used four LTC2216s, but the AD9265s
support higher clock rates with less power consumption, and both of those
attributes were important this time around.

And they work in space, should one care about that.. They also have nice low clock input noise.
(i.e. the SNR isn't too degraded from the ideal, compared to some other fast ADCs).

I am pretty sure I could design something like the PhaseStation as well.
The working principle is easy and can be explained on a napkin in 5

minutes.

But getting it to this remarkable perfomrance? Not without a lot of
trial and error. And even then, I wouldn't be sure.

I don't think there's any way to avoid the trial-and-error part unless you
have the luxury of an unlimited ceiling for both the R&D budget and the
target retail price, and maybe not even then. One reason it took longer
than expected to ship the 53100A was that a lot of lessons that I thought
had been adequately learned on the 5330A/3120A project didn't pay off when
different ADCs were used, and when the carrier and offset frequency
requirements grew by 6x and 10x respectively.
With the TimePod, for example, noise and spur performance weren't strongly
influenced by ADC clock distribution. On PhaseStation, that particular
"unlearned lesson" cost me a respin.

That is a real lesson - It's one that people doing their first low noise systems get burned by (do NOT run your clock signal from your quiet oscillator through the FPGA, and yes, that fancy fast clock driver might actually degrade performance because it has a 1GHz BW and so does the clock input on the ADC...)

And then, getting the data reliably out of the ADC into the FPGA, and synchronized across multiple channels. That particular part doesn't guarantee the startup state of the internal pipeline.

Keeping parts and manufacturing costs under control was also more difficult
than anticipated. Another lesson that wasn't learned soon enough was that a
design with four or five internal PCBs ends up being much more expensive
than one that uses only two, even if the total board area is similar. We
had to increase the price twice to maintain standard T&M industry margins,
and (having just come back from visiting Said and Giovanni at Jackson Labs)
that's about to happen again. The original vision of a four-figure price
tag was unrealistic, and that's definitely a lesson for next time.

is that because of connectors and interfaces?
Or because of "unit test" time and process?

I know that for space stuff, all on one board or in one box is cheaper than breaking it up, particularly for RF systems. Because if it's individual widgets, everyone wants individual test data at the widget level, before you combine them into superwidget assemblies.

If you are building an oscillator, you run into the same thing. Part of the issue
is simply that each board has some sort of testing / minimum charge. Split
the board into quarters and the price goes up significantly. As soon as you
set it up for assembly, you hit the same sort of cost issues. It then goes into
some sort of test process … cost goes up yet again ….

Bob

-- john, KE5FX
Miles Design LLC / Jackson Labs Technologies, Inc.

time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
and follow the instructions there.

Hi > On Mar 24, 2020, at 7:31 PM, jimlux <jimlux@earthlink.net> wrote: > > On 3/24/20 2:17 PM, John Miles wrote: >>>> It would be interesting to know what ADC was used and if there's an >>>> SDR-board out there that uses the same ADC. >>> >>> Uh.. I remember John telling me what ADC it was, but I forgot, sorry. >> It uses four AD9265s. The TimePod used four LTC2216s, but the AD9265s >> support higher clock rates with less power consumption, and both of those >> attributes were important this time around. > > And they work in space, should one care about that.. They also have nice low clock input noise. > (i.e. the SNR isn't too degraded from the ideal, compared to some other fast ADCs). > > >>> I am pretty sure I could design something like the PhaseStation as well. >>> The working principle is easy and can be explained on a napkin in 5 >> minutes. >>> But getting it to this remarkable perfomrance? Not without a lot of >>> trial and error. And even then, I wouldn't be sure. >> I don't think there's any way to avoid the trial-and-error part unless you >> have the luxury of an unlimited ceiling for both the R&D budget and the >> target retail price, and maybe not even then. One reason it took longer >> than expected to ship the 53100A was that a lot of lessons that I *thought* >> had been adequately learned on the 5330A/3120A project didn't pay off when >> different ADCs were used, and when the carrier and offset frequency >> requirements grew by 6x and 10x respectively. >> With the TimePod, for example, noise and spur performance weren't strongly >> influenced by ADC clock distribution. On PhaseStation, that particular >> "unlearned lesson" cost me a respin. > > That is a real lesson - It's one that people doing their first low noise systems get burned by (do NOT run your clock signal from your quiet oscillator through the FPGA, and yes, that fancy fast clock driver might actually degrade performance because it has a 1GHz BW and so does the clock input on the ADC...) > > And then, getting the data reliably out of the ADC into the FPGA, and synchronized across multiple channels. That particular part doesn't guarantee the startup state of the internal pipeline. > > > >> Keeping parts and manufacturing costs under control was also more difficult >> than anticipated. Another lesson that wasn't learned soon enough was that a >> design with four or five internal PCBs ends up being much more expensive >> than one that uses only two, even if the total board area is similar. We >> had to increase the price twice to maintain standard T&M industry margins, >> and (having just come back from visiting Said and Giovanni at Jackson Labs) >> that's about to happen again. The original vision of a four-figure price >> tag was unrealistic, and that's definitely a lesson for next time. > > is that because of connectors and interfaces? > Or because of "unit test" time and process? > > I know that for space stuff, all on one board or in one box is cheaper than breaking it up, particularly for RF systems. Because if it's individual widgets, everyone wants individual test data at the widget level, before you combine them into superwidget assemblies. If you are building an oscillator, you run into the same thing. Part of the issue is simply that each board has some sort of testing / minimum charge. Split the board into quarters and the price goes up significantly. As soon as you set it up for assembly, you hit the same sort of cost issues. It then goes into some sort of test process … cost goes up yet again …. Bob > > > >> -- john, KE5FX >> Miles Design LLC / Jackson Labs Technologies, Inc. >> _______________________________________________ >> time-nuts mailing list -- time-nuts@lists.febo.com >> To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com >> and follow the instructions there. > > > _______________________________________________ > time-nuts mailing list -- time-nuts@lists.febo.com > To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com > and follow the instructions there.

K

kb8tq@n1k.org

Wed, Mar 25, 2020 4:45 PM

Hi

So, here we have a couple of plots of a Clifton Labs Z10000 amplifier board. It's a part that several list members (including myself)
have recommended using. The board has the "stock" high input impedance and has been modified for 0 db gain (470 ohm resistor so
just over 0 db ...). There is a 6 db pad between the splitter and the amp to terminate things. The run is fairly short so the data is a bit rough.
For a better look, an overnight run would show a bit more detail.

Phase noise looks pretty good. ADEV has some weird "stuff" going on. Time to start tearing the board apart to see what's wrong with it?
Maybe there's some noise in those resistors .... let's go !!!!

Well..... maybe not so much. If you go back and dig up the original plots in this thread, the ADEV is essentially at the "noise
floor" of the measurement system. There are sure to be some wobbles in a shorter ADEV run so it's not a 1:1 sort of thing.
Phase noise wise, everything from about 80 Hz and lower is at noise floor. The data out at 100 KHz offset suggests that for a low
phase noise system, this board would degrade the typical 10811 by a slight bit "wideband".

Since noise floor likely changes with things like drive level and frequency, to be 100% sure of the floor, one would need to repeat the original
test at this frequency and these levels. I'm not that ambitious 😊 What I have tells me pretty well when I've hit the limit. It keeps me from
going crazy "debugging" a board that actually does not have a problem. (or if there's a problem, my quick test can't see it )

Some other Z10000 trivia:

If you drive this board so it has a couple db more output, it goes into clipping. When that happens .... yuck. Noise and ADEV both are massively
impacted. You very much do not want to overdrive this board. (This is also true of most amplifiers) At ~14 dbm out at 5 MHz you are in clipping.
I would stick with 12 dbm or less (at 5 MHz ... who knows about other frequencies ...).

Dropping gain to zero db with the resistors on the board is better than doing the same with a pad on the input. The wideband phase noise is a bit
better when done with the resistors. Very much like the front end on a radio ....

Fun !!!

Bob

-----Original Message-----
From: time-nuts time-nuts-bounces@lists.febo.com On Behalf Of jimlux
Sent: Tuesday, March 24, 2020 7:31 PM
To: time-nuts@lists.febo.com
Subject: Re: [time-nuts] Noise Floor

On 3/24/20 2:17 PM, John Miles wrote:

It would be interesting to know what ADC was used and if there's an
SDR-board out there that uses the same ADC.

Uh.. I remember John telling me what ADC it was, but I forgot, sorry.

Hi So, here we have a couple of plots of a Clifton Labs Z10000 amplifier board. It's a part that several list members (including myself) have recommended using. The board has the "stock" high input impedance and has been modified for 0 db gain (470 ohm resistor so just over 0 db ...). There is a 6 db pad between the splitter and the amp to terminate things. The run is fairly short so the data is a bit rough. For a better look, an overnight run would show a bit more detail. Phase noise looks pretty good. ADEV has some weird "stuff" going on. Time to start tearing the board apart to see what's wrong with it? Maybe there's some noise in those resistors .... let's go !!!! Well..... maybe not so much. If you go back and dig up the original plots in this thread, the ADEV is *essentially* at the "noise floor" of the measurement system. There are sure to be some wobbles in a shorter ADEV run so it's not a 1:1 sort of thing. Phase noise wise, everything from about 80 Hz and lower is at noise floor. The data out at 100 KHz offset suggests that for a low phase noise system, this board would degrade the typical 10811 by a slight bit "wideband". Since noise floor likely changes with things like drive level and frequency, to be 100% sure of the floor, one would need to repeat the original test at this frequency and these levels. I'm not that ambitious 😊 What I have tells me pretty well when I've hit the limit. It keeps me from going crazy "debugging" a board that actually does not have a problem. (or if there's a problem, my quick test can't see it ) Some other Z10000 trivia: If you drive this board so it has a couple db more output, it goes into clipping. When that happens .... yuck. Noise and ADEV both are massively impacted. You very much do *not* want to overdrive this board. (This is also true of most amplifiers) At ~14 dbm out at 5 MHz you are in clipping. I would stick with 12 dbm or less (at 5 MHz ... who knows about other frequencies ...). Dropping gain to zero db with the resistors on the board is better than doing the same with a pad on the input. The wideband phase noise is a bit better when done with the resistors. Very much like the front end on a radio .... Fun !!! Bob -----Original Message----- From: time-nuts <time-nuts-bounces@lists.febo.com> On Behalf Of jimlux Sent: Tuesday, March 24, 2020 7:31 PM To: time-nuts@lists.febo.com Subject: Re: [time-nuts] Noise Floor On 3/24/20 2:17 PM, John Miles wrote: >>> It would be interesting to know what ADC was used and if there's an >>> SDR-board out there that uses the same ADC. >> >> Uh.. I remember John telling me what ADC it was, but I forgot, sorry. >

TK

Taka Kamiya

Wed, Mar 25, 2020 6:49 PM

I've been playing around with Clifton amplifier as well. Mine, input is terminated with 50 ohm register, and rest is unmodified, so it has 6dB gain. I have a 10dB pad on input side. I, too, noticed there will be a severe clipping with driving it too hard. I plan to zero the gain and retest. Without proper termination on input side, it showed phantom gain of 10dB.....?
I stayed conservative and output is 7dBm. I with there was a little more room there.... Looks pretty clean spectral density wise. (frequency is 10MHz)

(Mr.) Taka Kamiya
KB4EMF / ex JF2DKG

On Wednesday, March 25, 2020, 2:00:08 PM EDT, kb8tq@n1k.org <kb8tq@n1k.org> wrote:

Hi

So, here we have a couple of plots of a Clifton Labs Z10000 amplifier board. It's a part that several list members (including myself)
have recommended using. The board has the "stock" high input impedance and has been modified for 0 db gain (470 ohm resistor so
just over 0 db ...). There is a 6 db pad between the splitter and the amp to terminate things. The run is fairly short so the data is a bit rough.
For a better look, an overnight run would show a bit more detail.

Phase noise looks pretty good. ADEV has some weird "stuff" going on. Time to start tearing the board apart to see what's wrong with it?
Maybe there's some noise in those resistors .... let's go !!!!

Well..... maybe not so much. If you go back and dig up the original plots in this thread, the ADEV is essentially at the "noise
floor" of the measurement system. There are sure to be some wobbles in a shorter ADEV run so it's not a 1:1 sort of thing.
Phase noise wise, everything from about 80 Hz and lower is at noise floor. The data out at 100 KHz offset suggests that for a low
phase noise system, this board would degrade the typical 10811 by a slight bit "wideband".

Since noise floor likely changes with things like drive level and frequency, to be 100% sure of the floor, one would need to repeat the original
test at this frequency and these levels. I'm not that ambitious 😊 What I have tells me pretty well when I've hit the limit. It keeps me from
going crazy "debugging" a board that actually does not have a problem. (or if there's a problem, my quick test can't see it )

Some other Z10000 trivia:

If you drive this board so it has a couple db more output, it goes into clipping. When that happens .... yuck. Noise and ADEV both are massively
impacted. You very much do not want to overdrive this board. (This is also true of most amplifiers) At ~14 dbm out at 5 MHz you are in clipping.
I would stick with 12 dbm or less (at 5 MHz ... who knows about other frequencies ...).

Dropping gain to zero db with the resistors on the board is better than doing the same with a pad on the input. The wideband phase noise is a bit
better when done with the resistors. Very much like the front end on a radio ....

Fun !!!

Bob

-----Original Message-----
From: time-nuts time-nuts-bounces@lists.febo.com On Behalf Of jimlux
Sent: Tuesday, March 24, 2020 7:31 PM
To: time-nuts@lists.febo.com
Subject: Re: [time-nuts] Noise Floor

On 3/24/20 2:17 PM, John Miles wrote:

It would be interesting to know what ADC was used and if there's an
SDR-board out there that uses the same ADC.

Uh.. I remember John telling me what ADC it was, but I forgot, sorry.

time-nuts mailing list -- time-nuts@lists.febo.com
To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com
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I've been playing around with Clifton amplifier as well. Mine, input is terminated with 50 ohm register, and rest is unmodified, so it has 6dB gain. I have a 10dB pad on input side. I, too, noticed there will be a severe clipping with driving it too hard. I plan to zero the gain and retest. Without proper termination on input side, it showed phantom gain of 10dB.....? I stayed conservative and output is 7dBm. I with there was a little more room there.... Looks pretty clean spectral density wise. (frequency is 10MHz) --------------------------------------- (Mr.) Taka Kamiya KB4EMF / ex JF2DKG On Wednesday, March 25, 2020, 2:00:08 PM EDT, kb8tq@n1k.org <kb8tq@n1k.org> wrote: Hi So, here we have a couple of plots of a Clifton Labs Z10000 amplifier board. It's a part that several list members (including myself) have recommended using. The board has the "stock" high input impedance and has been modified for 0 db gain (470 ohm resistor so just over 0 db ...). There is a 6 db pad between the splitter and the amp to terminate things. The run is fairly short so the data is a bit rough. For a better look, an overnight run would show a bit more detail. Phase noise looks pretty good. ADEV has some weird "stuff" going on. Time to start tearing the board apart to see what's wrong with it? Maybe there's some noise in those resistors .... let's go !!!! Well..... maybe not so much. If you go back and dig up the original plots in this thread, the ADEV is *essentially* at the "noise floor" of the measurement system. There are sure to be some wobbles in a shorter ADEV run so it's not a 1:1 sort of thing. Phase noise wise, everything from about 80 Hz and lower is at noise floor. The data out at 100 KHz offset suggests that for a low phase noise system, this board would degrade the typical 10811 by a slight bit "wideband". Since noise floor likely changes with things like drive level and frequency, to be 100% sure of the floor, one would need to repeat the original test at this frequency and these levels. I'm not that ambitious 😊 What I have tells me pretty well when I've hit the limit. It keeps me from going crazy "debugging" a board that actually does not have a problem. (or if there's a problem, my quick test can't see it ) Some other Z10000 trivia: If you drive this board so it has a couple db more output, it goes into clipping. When that happens .... yuck. Noise and ADEV both are massively impacted. You very much do *not* want to overdrive this board. (This is also true of most amplifiers) At ~14 dbm out at 5 MHz you are in clipping. I would stick with 12 dbm or less (at 5 MHz ... who knows about other frequencies ...). Dropping gain to zero db with the resistors on the board is better than doing the same with a pad on the input. The wideband phase noise is a bit better when done with the resistors. Very much like the front end on a radio .... Fun !!! Bob -----Original Message----- From: time-nuts <time-nuts-bounces@lists.febo.com> On Behalf Of jimlux Sent: Tuesday, March 24, 2020 7:31 PM To: time-nuts@lists.febo.com Subject: Re: [time-nuts] Noise Floor On 3/24/20 2:17 PM, John Miles wrote: >>> It would be interesting to know what ADC was used and if there's an >>> SDR-board out there that uses the same ADC. >> >> Uh.. I remember John telling me what ADC it was, but I forgot, sorry. > _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.

K

kb8tq@n1k.org

Wed, Mar 25, 2020 9:21 PM

Hi

Gain without an input termination will very much depend on the source you are driving it from. With a
"proper" 50 ohm source, the gain will be 6 db high without the input resistor. If it's got more gain than
that, your source is not 50 ohms. There are a lot of OCXO's out there that are not "true" 50 ohm sources.

Input termination or not depends a lot on what you are going to use it for. In my case, I'm after a high
input impedance to low output impedance conversion. I need to deal with some gear that was made back
before 50 ohms was "how it's done".

Bob

-----Original Message-----
From: time-nuts time-nuts-bounces@lists.febo.com On Behalf Of Taka Kamiya via time-nuts
Sent: Wednesday, March 25, 2020 2:49 PM
To: Discussion of precise time and frequency measurement time-nuts@lists.febo.com
Cc: Taka Kamiya tkamiya9@yahoo.com
Subject: Re: [time-nuts] Noise Floor

I've been playing around with Clifton amplifier as well. Mine, input is terminated with 50 ohm register, and rest is unmodified, so it has 6dB gain. I have a 10dB pad on input side. I, too, noticed there will be a severe clipping with driving it too hard. I plan to zero the gain and retest. Without proper termination on input side, it showed phantom gain of 10dB.....?
I stayed conservative and output is 7dBm. I with there was a little more room there.... Looks pretty clean spectral density wise. (frequency is 10MHz)

(Mr.) Taka Kamiya
KB4EMF / ex JF2DKG

On Wednesday, March 25, 2020, 2:00:08 PM EDT, kb8tq@n1k.org <kb8tq@n1k.org> wrote:

Hi

So, here we have a couple of plots of a Clifton Labs Z10000 amplifier board. It's a part that several list members (including myself)
have recommended using. The board has the "stock" high input impedance and has been modified for 0 db gain (470 ohm resistor so
just over 0 db ...). There is a 6 db pad between the splitter and the amp to terminate things. The run is fairly short so the data is a bit rough.
For a better look, an overnight run would show a bit more detail.

Phase noise looks pretty good. ADEV has some weird "stuff" going on. Time to start tearing the board apart to see what's wrong with it?
Maybe there's some noise in those resistors .... let's go !!!!

Well..... maybe not so much. If you go back and dig up the original plots in this thread, the ADEV is essentially at the "noise
floor" of the measurement system. There are sure to be some wobbles in a shorter ADEV run so it's not a 1:1 sort of thing.
Phase noise wise, everything from about 80 Hz and lower is at noise floor. The data out at 100 KHz offset suggests that for a low
phase noise system, this board would degrade the typical 10811 by a slight bit "wideband".

Since noise floor likely changes with things like drive level and frequency, to be 100% sure of the floor, one would need to repeat the original
test at this frequency and these levels. I'm not that ambitious 😊 What I have tells me pretty well when I've hit the limit. It keeps me from
going crazy "debugging" a board that actually does not have a problem. (or if there's a problem, my quick test can't see it )

Some other Z10000 trivia:

If you drive this board so it has a couple db more output, it goes into clipping. When that happens .... yuck. Noise and ADEV both are massively
impacted. You very much do not want to overdrive this board. (This is also true of most amplifiers) At ~14 dbm out at 5 MHz you are in clipping.
I would stick with 12 dbm or less (at 5 MHz ... who knows about other frequencies ...).

Dropping gain to zero db with the resistors on the board is better than doing the same with a pad on the input. The wideband phase noise is a bit
better when done with the resistors. Very much like the front end on a radio ....

Fun !!!

Bob

-----Original Message-----
From: time-nuts time-nuts-bounces@lists.febo.com On Behalf Of jimlux
Sent: Tuesday, March 24, 2020 7:31 PM
To: time-nuts@lists.febo.com
Subject: Re: [time-nuts] Noise Floor

On 3/24/20 2:17 PM, John Miles wrote:

It would be interesting to know what ADC was used and if there's an
SDR-board out there that uses the same ADC.

Uh.. I remember John telling me what ADC it was, but I forgot, sorry.

time-nuts mailing list -- time-nuts@lists.febo.com
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and follow the instructions there.

Hi Gain without an input termination will very much depend on the source you are driving it from. With a "proper" 50 ohm source, the gain will be 6 db high without the input resistor. If it's got more gain than that, your source is not 50 ohms. There are a lot of OCXO's out there that are not "true" 50 ohm sources. Input termination or not depends a *lot* on what you are going to use it for. In my case, I'm after a high input impedance to low output impedance conversion. I need to deal with some gear that was made back before 50 ohms was "how it's done". Bob -----Original Message----- From: time-nuts <time-nuts-bounces@lists.febo.com> On Behalf Of Taka Kamiya via time-nuts Sent: Wednesday, March 25, 2020 2:49 PM To: Discussion of precise time and frequency measurement <time-nuts@lists.febo.com> Cc: Taka Kamiya <tkamiya9@yahoo.com> Subject: Re: [time-nuts] Noise Floor I've been playing around with Clifton amplifier as well. Mine, input is terminated with 50 ohm register, and rest is unmodified, so it has 6dB gain. I have a 10dB pad on input side. I, too, noticed there will be a severe clipping with driving it too hard. I plan to zero the gain and retest. Without proper termination on input side, it showed phantom gain of 10dB.....? I stayed conservative and output is 7dBm. I with there was a little more room there.... Looks pretty clean spectral density wise. (frequency is 10MHz) --------------------------------------- (Mr.) Taka Kamiya KB4EMF / ex JF2DKG On Wednesday, March 25, 2020, 2:00:08 PM EDT, kb8tq@n1k.org <kb8tq@n1k.org> wrote: Hi So, here we have a couple of plots of a Clifton Labs Z10000 amplifier board. It's a part that several list members (including myself) have recommended using. The board has the "stock" high input impedance and has been modified for 0 db gain (470 ohm resistor so just over 0 db ...). There is a 6 db pad between the splitter and the amp to terminate things. The run is fairly short so the data is a bit rough. For a better look, an overnight run would show a bit more detail. Phase noise looks pretty good. ADEV has some weird "stuff" going on. Time to start tearing the board apart to see what's wrong with it? Maybe there's some noise in those resistors .... let's go !!!! Well..... maybe not so much. If you go back and dig up the original plots in this thread, the ADEV is *essentially* at the "noise floor" of the measurement system. There are sure to be some wobbles in a shorter ADEV run so it's not a 1:1 sort of thing. Phase noise wise, everything from about 80 Hz and lower is at noise floor. The data out at 100 KHz offset suggests that for a low phase noise system, this board would degrade the typical 10811 by a slight bit "wideband". Since noise floor likely changes with things like drive level and frequency, to be 100% sure of the floor, one would need to repeat the original test at this frequency and these levels. I'm not that ambitious 😊 What I have tells me pretty well when I've hit the limit. It keeps me from going crazy "debugging" a board that actually does not have a problem. (or if there's a problem, my quick test can't see it ) Some other Z10000 trivia: If you drive this board so it has a couple db more output, it goes into clipping. When that happens .... yuck. Noise and ADEV both are massively impacted. You very much do *not* want to overdrive this board. (This is also true of most amplifiers) At ~14 dbm out at 5 MHz you are in clipping. I would stick with 12 dbm or less (at 5 MHz ... who knows about other frequencies ...). Dropping gain to zero db with the resistors on the board is better than doing the same with a pad on the input. The wideband phase noise is a bit better when done with the resistors. Very much like the front end on a radio .... Fun !!! Bob -----Original Message----- From: time-nuts <time-nuts-bounces@lists.febo.com> On Behalf Of jimlux Sent: Tuesday, March 24, 2020 7:31 PM To: time-nuts@lists.febo.com Subject: Re: [time-nuts] Noise Floor On 3/24/20 2:17 PM, John Miles wrote: >>> It would be interesting to know what ADC was used and if there's an >>> SDR-board out there that uses the same ADC. >> >> Uh.. I remember John telling me what ADC it was, but I forgot, sorry. > _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there. _______________________________________________ time-nuts mailing list -- time-nuts@lists.febo.com To unsubscribe, go to http://lists.febo.com/mailman/listinfo/time-nuts_lists.febo.com and follow the instructions there.

CS

Charles Steinmetz

Wed, Mar 25, 2020 9:22 PM

Taka Kamiya wrote:

I've been playing around with Clifton amplifier as well. Mine, input is terminated with 50 ohm register, and rest is unmodified, so it has 6dB gain. I have a 10dB pad on input side. I, too, noticed there will be a severe clipping with driving it too hard. * * * I with there was a little more room there....

Bob wrote:

Maybe there's some noise in those resistors
Well..... maybe not so much.

If you drive this board so it has a couple db more output, it goes into clipping. When that happens .... yuck.
Noise and ADEV both are massively impacted.
You very much do not want to overdrive this board. * * *
I would stick with 12 dbm or less

You can buy some headroom by raising the supply voltage. There is an
on-card LM78L09 9v voltage regulator (U902) that can safely be raised to
12v (LM78L12). This will get you cleanly to and a bit past the
traditional +13 dBm (1v rms) standard reference level. Of course, you
will need to make sure the raw supply voltage is >15v.

As to noise, the 200 ohm resistor on the opamp's noninverting input
(R901) accounts for nearly 6dB of the amplifier noise (assuming an
effective source impedance of 50 ohms). Reducing this to, say, 33 ohms
will lower the noise floor a few dB.

Finally, the state of CFB video amplifier development has advanced
dramatically in the 20 years since the AD8007 was introduced. New
amplifiers with supply voltage ratings up to 36v are available (allowing
about 10dB greater headroom than the 8007), and many of the newer opamps
clip much more gracefully than the 8007 when you do hit the limit (but
you really want not to do that in any measurement application).

Many of these new CFB amplifiers have been discussed here on the list,
and each has its own fans. One I like that doesn't get mentioned much
is the LME49713. It is discontinued, but still available from Rochester
Electronics and others. But there are lots of good choices.

Best regards,

Charles

Taka Kamiya wrote: > I've been playing around with Clifton amplifier as well. Mine, input is terminated with 50 ohm register, and rest is unmodified, so it has 6dB gain. I have a 10dB pad on input side. I, too, noticed there will be a severe clipping with driving it too hard. * * * I with there was a little more room there.... Bob wrote: >> Maybe there's some noise in those resistors >> Well..... maybe not so much. >> >> If you drive this board so it has a couple db more output, it goes into clipping. When that happens .... yuck. >> Noise and ADEV both are massively impacted. >> You very much do *not* want to overdrive this board. * * * >> I would stick with 12 dbm or less You can buy some headroom by raising the supply voltage. There is an on-card LM78L09 9v voltage regulator (U902) that can safely be raised to 12v (LM78L12). This will get you cleanly to and a bit past the traditional +13 dBm (1v rms) standard reference level. Of course, you will need to make sure the raw supply voltage is >15v. As to noise, the 200 ohm resistor on the opamp's noninverting input (R901) accounts for nearly 6dB of the amplifier noise (assuming an effective source impedance of 50 ohms). Reducing this to, say, 33 ohms will lower the noise floor a few dB. Finally, the state of CFB video amplifier development has advanced dramatically in the 20 years since the AD8007 was introduced. New amplifiers with supply voltage ratings up to 36v are available (allowing about 10dB greater headroom than the 8007), and many of the newer opamps clip much more gracefully than the 8007 when you do hit the limit (but you really want not to do that in any measurement application). Many of these new CFB amplifiers have been discussed here on the list, and each has its own fans. One I like that doesn't get mentioned much is the LME49713. It is discontinued, but still available from Rochester Electronics and others. But there are lots of good choices. Best regards, Charles

JM

John Miles

Wed, Mar 25, 2020 10:32 PM

-----Original Message-----
From: time-nuts [mailto:time-nuts-bounces@lists.febo.com] On Behalf Of
kb8tq@n1k.org
Sent: Wednesday, March 25, 2020 9:46 AM
To: 'Discussion of precise time and frequency measurement'
Subject: Re: [time-nuts] Noise Floor

Phase noise looks pretty good. ADEV has some weird "stuff" going on. Time
to start tearing the board apart to see what's wrong with it?
Maybe there's some noise in those resistors .... let's go !!!!

Resistor noise won't normally show up on plots at this level, but it does look like there is some kind of periodic disturbance near 1 Hz. Could be a thermal artifact due to convection currents on the board, or possibly a case where large undamped LC components have been used in a power supply filter or bias network.

I'd be more likely to suspect crosstalk from a nearby 5 MHz source that isn't quite on the same frequency, which should be easy enough to rule out. Poor cable shield integrity can also encourage this type of artifact to appear, even in the absence of an obvious interferer.

On the phase noise plot, the 53100A thinks it's an instrument spur and is removing it. It's very unlikely to be one, but this process will never be 100% reliable, especially in short-duration measurements. You can see a suspiciously-flat segment centered at about 0.9 Hz, which often indicates that a spur is being suppressed automatically. The stability data doesn't undergo any automatic spur detection or removal, so when you see ripple in the ADEV plot that doesn't correspond to an obvious spur on the PN plot, it's a good idea to either let the measurement run longer or set the 'Spur min offset' value to 10 Hz or so.

-- john

> -----Original Message----- > From: time-nuts [mailto:time-nuts-bounces@lists.febo.com] On Behalf Of > kb8tq@n1k.org > Sent: Wednesday, March 25, 2020 9:46 AM > To: 'Discussion of precise time and frequency measurement' > Subject: Re: [time-nuts] Noise Floor > > Phase noise looks pretty good. ADEV has some weird "stuff" going on. Time > to start tearing the board apart to see what's wrong with it? > Maybe there's some noise in those resistors .... let's go !!!! > Resistor noise won't normally show up on plots at this level, but it does look like there is some kind of periodic disturbance near 1 Hz. Could be a thermal artifact due to convection currents on the board, or possibly a case where large undamped LC components have been used in a power supply filter or bias network. I'd be more likely to suspect crosstalk from a nearby 5 MHz source that isn't quite on the same frequency, which should be easy enough to rule out. Poor cable shield integrity can also encourage this type of artifact to appear, even in the absence of an obvious interferer. On the phase noise plot, the 53100A thinks it's an instrument spur and is removing it. It's very unlikely to be one, but this process will never be 100% reliable, especially in short-duration measurements. You can see a suspiciously-flat segment centered at about 0.9 Hz, which often indicates that a spur is being suppressed automatically. The stability data doesn't undergo any automatic spur detection or removal, so when you see ripple in the ADEV plot that doesn't correspond to an obvious spur on the PN plot, it's a good idea to either let the measurement run longer or set the 'Spur min offset' value to 10 Hz or so. -- john