In a message dated 12/19/2007 10:38:54 Pacific Standard Time,
boyscout@gmail.com writes:

Hi Matt,

in my opinion, you would probably introduce some thermal noise through this
50KOhm equivalent resistor while the PLL is not operating. Noise could maybe
be  reduced if there is a cap to ground on this divider (this cap being part of
the  loop filter).

The PLL bandwidth depends solely on the phase noise of your 10MHz source
versus your 100MHz oscillator. If the 10MHz source is better at say 100Hz  offset
(better by more than 20dB) then the loop bandwidth should  be more than
100Hz, so that the PLL can actually reduce the phase noise of  your 100MHz
oscillator.

At 100Hz offset, you say you have -68dBc/Hz at 100MHz. This calculates to
-88dBc/Hz at 100Hz offset for the 10MHz source (excluding the PLL chip and
loop-filter noise). You may want to check the noise performance of the PLL on  the
ADI website's PLL simulator.

So if you have much better than -88dBc/Hz at 100Hz on your 10MHz oscillator
(not hard to achieve, many oscillators have <-140dBc/Hz at 100Hz already)
then you would be wasting performance with a <100Hz loop filter, and you  may
want to do a 1KHz or even wider loop filter or so. But if you don't  know the
10MHz source's performance, it is probably best to be safe and use  10Hz, or
100Hz loop filter BW.

A good spectrum analyzer (such as HP 8560B/E etc with the phase-noise
software option) should allow you to measure <-68dBc/Hz noise at 100Hz offset  at
100MHz, so you can check what BW results in the overall lowest noise.

In short, if you want to maximize your systems performance, then loop
bandwidth depends on the performance of the 10MHz versus the 100MHz  oscillator for
close-in phase noise.

To do the math, subtract 20log(100/10) = -20dB from the noise of the 100MHz
oscillator to get the equivalent noise energy for the 10MHz oscillator (at the
same frequency offset).

Hope this makes sense,
bye,
Said

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As long as you don't think it will affect stability when in lock, then I am ok.

Yes, I understand all the math.  I just don't know what to expect from
the 10 MHz references people will plug in.  Clearly if they plug in a
Fury, I should use a wide bandwidth, but who knows what else they'll
use...

Thanks,
Matt

True, the specs on that 100 MHz VCXO are not what you'd call high-end.
Pretty much any decent SA will measure its noise directly between 100 Hz and
1 kHz.  An 8568A/B running my phase-noise app will do it for about 1/4 the
cost of an 8560E.

With a noisy VCXO like that, I would certainly favor wider loop bandwidths
over narrower ones.  1 kHz would be the minimum I'd consider using.
Anyone using an external 10 MHz clock is probably getting it from something
like a Thunderbolt, Z3801, or homebrew GPS clock with a decent 10 MHz OCXO.

Count on the external 10 MHz clock coming in at -135 dBc/Hz or better at 1
kHz, IMO, which when scaled to 100 MHz becomes -115 dBc/Hz at 1 kHz.  Your
VCXO is at -98 there, so it will certainly benefit from a loop bandwidth
that wide.  By 10 kHz, though, your VCXO is as clean as a 10811A scaled to
100 MHz.  So I wouldn't go much wider than 3-5 kHz under any conditions, for
fear of letting a lower-quality 10 MHz source make things worse.

Do not use a 50K resistor at your charge-pump output, though!  That will
cause the PLL to 'hunt' continually, adding reference sidebands to the
output.  I would use a JFET or CMOS analog switch, or even a relay, to
disconnect the charge pump and switch in the half-rail fixed supply.

-- john, KE5FX

On Dec 19, 2007 12:06 PM, John Miles jmiles@pop.net wrote:

That is good information.  My other fear is that the user's 10 MHz
will pick up some 60 Hz on the way to my system, but I suppose there
is no way I want to be narrower than 60 Hz on my loop bandwidth.

That is what I was afraid of.  Thanks for the warning.

Matt

Yeah, not without a much-better OCXO than that.

Of course, if your other system constraints are such that the VCXO's noise
is not important, it won't pay to discipline it in a wideband loop.  If you
don't need the cleanup effect, a narrowband loop is preferable for just that
reason (spur suppression).

You could always try it and see what happens, but at least in an ordinary RF
PLL, you'd ordinarily go out of your way to avoid sourcing or sinking
current from the charge pump.

Your reference frequency is very far from the loop bandwidth in this case
(10 MHz versus ~1 kHz), so you might get away with the resistive-divider
idea.  It wouldn't be the best practice in the general case, though.

(I wouldn't worry about resistor noise either way, because the VCXO's tuning
sensitivity isn't very high.)

-- john, KE5FX

... er, TCXO.

-- john, KE5FX

... er, VCXO.

/outta coffee