while executing

Hi all my next step in exploring the rfnoc and its capabilities is to get a minimal working example of a custom rfnoc block (2 settings register, and a gain/offset function). I could copy and adjust an xml file, so there is my "new" custom block showed in gnuradio. But as I tried to create a vivado project with a clean repository copy of "fpga-src" I get some problems (without any customizations): I couldn't build the source and I wasn't also able to create a new vivado project (with vivado version 2015.2 and 2015.4, same error): dsp@dsp-ThinkPad-T440p ~/rfnoc/src/uhd/fpga-src/usrp3/top/x300 $ make X310_RFNOC_HGS GUI=1 make -f Makefile.x300.inc bin NAME=X310_RFNOC_HGS ARCH=kintex7 PART_ID=xc7k410t/ffg900/-2 ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 RFNOC=1 X310=1 EXTRA_DEFS="ETH10G_PORT1=1 BUILD_1G=1 BUILD_10G=1 NO_DRAM_FIFOS=1 SRAM_FIFO_SIZE=16 RFNOC=1 X310=1" make[1]: Entering directory `/home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300' Vivado v2015.2 (64-bit) ======================================================== BUILDER: Building IP ten_gig_eth_pcs_pma ======================================================== BUILDER: Staging IP in build directory... Reserving IP location: /home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma BUILDER: Retargeting IP to part xc7k410tffg900-2... BUILDER: Building IP... WARNING: Default location for XILINX_VIVADO_HLS not found: ****** Vivado v2015.2 (64-bit) **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 **** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source /home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/../tools/scripts/viv_generate_ip.tcl # set xci_file $::env(XCI_FILE) ; # set part_name $::env(PART_NAME) ; # set gen_example_proj $::env(GEN_EXAMPLE) ; # set synth_ip $::env(SYNTH_IP) ; # set ip_name [file rootname [file tail $xci_file]] ; # file delete -force "$xci_file.out" # create_project -part $part_name -in_memory -ip # set_property target_simulator XSim [current_project] # add_files -norecurse -force $xci_file INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.2/data/ip'. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_funcsim.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.dcp'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.v'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_stub.vhdl'. Please regenerate to continue. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_funcsim.v'. Please regenerate to continue. WARNING: [IP_Flow 19-2162] IP 'ten_gig_eth_pcs_pma' is locked: * The IP Data in the repository is incompatible with the current instance (despite having identical Version and Revision). You will need to update the IP before viewing the customization and generating outputs. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. # reset_target all [get_files $xci_file] CRITICAL WARNING: [filemgmt 20-1366] Unable to reset target(s) for the following file is locked: /home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci Locked reason: * The IP Data in the repository is incompatible with the current instance (despite having identical Version and Revision). You will need to update the IP before viewing the customization and generating outputs. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. # puts "BUILDER: Generating IP Target..." BUILDER: Generating IP Target... # generate_target all [get_files $xci_file] CRITICAL WARNING: [filemgmt 20-1365] Unable to generate target(s) for the following file is locked: /home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci Locked reason: * The IP Data in the repository is incompatible with the current instance (despite having identical Version and Revision). You will need to update the IP before viewing the customization and generating outputs. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. # if [string match $synth_ip "1"] { # puts "BUILDER: Synthesizing IP Target..." # synth_ip [get_ips $ip_name] # } BUILDER: Synthesizing IP Target... INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.2/data/ip'. WARNING: [IP_Flow 19-3664] IP 'ten_gig_eth_pcs_pma' generated file not found '/home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma_funcsim.vhdl'. Please regenerate to continue. Command: synth_design -top ten_gig_eth_pcs_pma -part xc7k410tffg900-2 -mode out_of_context Starting synth_design WARNING: [IP_Flow 19-2162] IP 'ten_gig_eth_pcs_pma' is locked: * The IP Data in the repository is incompatible with the current instance (despite having identical Version and Revision). You will need to update the IP before viewing the customization and generating outputs. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. Attempting to get a license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7k410t' INFO: [Common 17-83] Releasing license: Synthesis 3 Infos, 2 Warnings, 0 Critical Warnings and 1 Errors encountered. synth_design failed ERROR: [Designutils 20-414] HRTInvokeSpec : No Verilog or VHDL sources specified ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Vivado 12-398] No designs are open ****** Webtalk v2015.2 (64-bit) **** SW Build 1266856 on Fri Jun 26 16:35:25 MDT 2015 **** IP Build 1264090 on Wed Jun 24 14:22:01 MDT 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source /home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/.Xil/Vivado-3846-dsp-ThinkPad-T440p/webtalk/labtool_webtalk.tcl -notrace while executing "webtalk_transmit -clientid 2364942285 -regid "174236156_177743796_210619486_449" -xml /home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410..." (file "/home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/.Xil/Vivado-3846-dsp-ThinkPad-T440p/webtalk/labtool_webtalk.tcl" line 26) INFO: [Common 17-206] Exiting Webtalk at Fri Apr 8 10:51:36 2016... INFO: [Vivado 12-3441] generate_netlist_ip - operation complete synth_ip: Time (s): cpu = 00:00:00.82 ; elapsed = 00:00:06 . Memory (MB): peak = 927.707 ; gain = 13.133 ; free physical = 5469 ; free virtual = 8870 # if [string match $gen_example_proj "1"] { # puts "BUILDER: Generating Example Design..." # open_example_project -force -dir . [get_ips $ip_name] # } BUILDER: Generating Example Design... ERROR: [Common 17-69] Command failed: * The IP Data in the repository is incompatible with the current instance (despite having identical Version and Revision). You will need to update the IP before viewing the customization and generating outputs. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. INFO: [Common 17-206] Exiting Vivado at Fri Apr 8 10:51:36 2016... Releasing IP location: /home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma make[1]: *** [/home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] Error 1 make[1]: Leaving directory `/home/dsp/rfnoc/src/uhd/fpga-src/usrp3/top/x300' make: *** [X310_RFNOC_HGS] Error 2 It seems that there is a IP-Version problem with the "ten_gig_eth_pc_pma" core. I tried both, with and without "GUI=1". No difference. But without a Vivado project I can't update the IP cores... How could I solve this? Or is there a possibility to get a existing vivado project with all project files? So this is my first question about custom blocks. The others are following. Thank you very much, best regards Patrick

Hi Patrick, What branch are you on? rfnoc-devel or rfnoc-ofdm? Did you run source setupenv.sh in the usrp3/top/x300/ directory? What is it output? Jonathon

I am also getting the same error. this is an attempt to build the base RFNOC HGS image with no change in the utilized blocks. I run source setupenv.sh --vivado-path=/home/sdr-dev/xilinx/Vivado which outputs the following Setting up X3x0 FPGA build environment (64-bit)... bash: /home/sdr-dev/xilinx/Vivado_HLS/2015.2/.settings64-Vivado_High_Level_Synthesis.sh: No such file or directory bash: /opt/Xilinx/DocNav/.settings64-DocNav.sh: No such file or directory - Vivado: Found (/home/sdr-dev/xilinx/Vivado/2015.2/bin) Environment successfully initialized. I then run the command make X310_RFNOC_HGS yielding a message saying INFO: [Common 17-206] Exiting Webtalk at Mon Apr 25 14:31:25 2016... INFO: [Vivado 12-3441] generate_netlist_ip - operation complete synth_ip: Time (s): cpu = 00:00:58 ; elapsed = 00:01:17 . Memory (MB): peak = 1857.766 ; gain = 970.414 ; free physical = 4787 ; free virtual = 14137 # if [string match $gen_example_proj "1"] { # puts "BUILDER: Generating Example Design..." # open_example_project -force -dir . [get_ips $ip_name] # } BUILDER: Generating Example Design... ERROR: [Common 17-69] Command failed: * The IP Data in the repository is incompatible with the current instance (despite having identical Version and Revision). You will need to update the IP before viewing the customization and generating outputs. * IP file '/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml' for IP 'ten_gig_eth_pcs_pma' contains stale content. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. INFO: [Common 17-206] Exiting Vivado at Mon Apr 25 14:31:25 2016... Releasing IP location: /home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma make[1]: *** [/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] Error 1 make[1]: Leaving directory `/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300' make: *** [X310_RFNOC_HGS] Error 2 On Sun, Apr 10, 2016 at 12:52 PM, Jonathon Pendlum via USRP-users < usrp-users@lists.ettus.com> wrote: > Hi Patrick, > > What branch are you on? rfnoc-devel or rfnoc-ofdm? Did you run source > setupenv.sh in the usrp3/top/x300/ directory? What is it output? > > > > Jonathon > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >

Hi James, Did you try running 'make cleanall' and building again? Jonathon On Mon, Apr 25, 2016 at 2:36 PM, James Wagner <jdwagnerjr@gmail.com> wrote: > I am also getting the same error. > > this is an attempt to build the base RFNOC HGS image with no change in the > utilized blocks. > > I run > > source setupenv.sh --vivado-path=/home/sdr-dev/xilinx/Vivado > > which outputs the following > > Setting up X3x0 FPGA build environment (64-bit)... > bash: > /home/sdr-dev/xilinx/Vivado_HLS/2015.2/.settings64-Vivado_High_Level_Synthesis.sh: > No such file or directory > bash: /opt/Xilinx/DocNav/.settings64-DocNav.sh: No such file or directory > - Vivado: Found (/home/sdr-dev/xilinx/Vivado/2015.2/bin) > > Environment successfully initialized. > > > > I then run the command > > make X310_RFNOC_HGS > > yielding a message saying > > > INFO: [Common 17-206] Exiting Webtalk at Mon Apr 25 14:31:25 2016... > INFO: [Vivado 12-3441] generate_netlist_ip - operation complete > synth_ip: Time (s): cpu = 00:00:58 ; elapsed = 00:01:17 . Memory (MB): > peak = 1857.766 ; gain = 970.414 ; free physical = 4787 ; free virtual = > 14137 > # if [string match $gen_example_proj "1"] { > # puts "BUILDER: Generating Example Design..." > # open_example_project -force -dir . [get_ips $ip_name] > # } > BUILDER: Generating Example Design... > ERROR: [Common 17-69] Command failed: * The IP Data in the repository is > incompatible with the current instance (despite having identical Version > and Revision). You will need to update the IP before viewing the > customization and generating outputs. > * IP file > '/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml' > for IP 'ten_gig_eth_pcs_pma' contains stale content. > Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl > command 'report_ip_status' for more information. > INFO: [Common 17-206] Exiting Vivado at Mon Apr 25 14:31:25 2016... > Releasing IP location: > /home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma > make[1]: *** > [/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] > Error 1 > make[1]: Leaving directory `/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300' > make: *** [X310_RFNOC_HGS] Error 2 > > > > > > On Sun, Apr 10, 2016 at 12:52 PM, Jonathon Pendlum via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi Patrick, >> >> What branch are you on? rfnoc-devel or rfnoc-ofdm? Did you run source >> setupenv.sh in the usrp3/top/x300/ directory? What is it output? >> >> >> >> Jonathon >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >

Johnathon, Thanks, 'make cleanall' seems to resolve the problem although 'make clean' does not. I noticed that both the original poster and I had 2015.4 so maybe this is an issue with it trying to use 2015.4 IP unless you force the script to clear all previous IP. On Tue, Apr 26, 2016 at 9:14 AM, Jonathon Pendlum < jonathon.pendlum@ettus.com> wrote: > Hi James, > > Did you try running 'make cleanall' and building again? > > > > Jonathon > > On Mon, Apr 25, 2016 at 2:36 PM, James Wagner <jdwagnerjr@gmail.com> > wrote: > >> I am also getting the same error. >> >> this is an attempt to build the base RFNOC HGS image with no change in >> the utilized blocks. >> >> I run >> >> source setupenv.sh --vivado-path=/home/sdr-dev/xilinx/Vivado >> >> which outputs the following >> >> Setting up X3x0 FPGA build environment (64-bit)... >> bash: >> /home/sdr-dev/xilinx/Vivado_HLS/2015.2/.settings64-Vivado_High_Level_Synthesis.sh: >> No such file or directory >> bash: /opt/Xilinx/DocNav/.settings64-DocNav.sh: No such file or directory >> - Vivado: Found (/home/sdr-dev/xilinx/Vivado/2015.2/bin) >> >> Environment successfully initialized. >> >> >> >> I then run the command >> >> make X310_RFNOC_HGS >> >> yielding a message saying >> >> >> INFO: [Common 17-206] Exiting Webtalk at Mon Apr 25 14:31:25 2016... >> INFO: [Vivado 12-3441] generate_netlist_ip - operation complete >> synth_ip: Time (s): cpu = 00:00:58 ; elapsed = 00:01:17 . Memory (MB): >> peak = 1857.766 ; gain = 970.414 ; free physical = 4787 ; free virtual = >> 14137 >> # if [string match $gen_example_proj "1"] { >> # puts "BUILDER: Generating Example Design..." >> # open_example_project -force -dir . [get_ips $ip_name] >> # } >> BUILDER: Generating Example Design... >> ERROR: [Common 17-69] Command failed: * The IP Data in the repository is >> incompatible with the current instance (despite having identical Version >> and Revision). You will need to update the IP before viewing the >> customization and generating outputs. >> * IP file >> '/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml' >> for IP 'ten_gig_eth_pcs_pma' contains stale content. >> Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl >> command 'report_ip_status' for more information. >> INFO: [Common 17-206] Exiting Vivado at Mon Apr 25 14:31:25 2016... >> Releasing IP location: >> /home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma >> make[1]: *** >> [/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] >> Error 1 >> make[1]: Leaving directory >> `/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300' >> make: *** [X310_RFNOC_HGS] Error 2 >> >> >> >> >> >> On Sun, Apr 10, 2016 at 12:52 PM, Jonathon Pendlum via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >>> Hi Patrick, >>> >>> What branch are you on? rfnoc-devel or rfnoc-ofdm? Did you run source >>> setupenv.sh in the usrp3/top/x300/ directory? What is it output? >>> >>> >>> >>> Jonathon >>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >> >

Correct, when the build uses a different Vivado version the old IP needs to be cleaned with 'make cleanall'. I'll see if we can modify the makefiles to make that unnecessary or at least less of a hassle. On Wed, Apr 27, 2016 at 1:27 PM, James Wagner <jdwagnerjr@gmail.com> wrote: > Johnathon, > Thanks, 'make cleanall' seems to resolve the problem although 'make clean' > does not. > > I noticed that both the original poster and I had 2015.4 so maybe this is > an issue with it trying to use 2015.4 IP unless you force the script to > clear all previous IP. > > On Tue, Apr 26, 2016 at 9:14 AM, Jonathon Pendlum < > jonathon.pendlum@ettus.com> wrote: > >> Hi James, >> >> Did you try running 'make cleanall' and building again? >> >> >> >> Jonathon >> >> On Mon, Apr 25, 2016 at 2:36 PM, James Wagner <jdwagnerjr@gmail.com> >> wrote: >> >>> I am also getting the same error. >>> >>> this is an attempt to build the base RFNOC HGS image with no change in >>> the utilized blocks. >>> >>> I run >>> >>> source setupenv.sh --vivado-path=/home/sdr-dev/xilinx/Vivado >>> >>> which outputs the following >>> >>> Setting up X3x0 FPGA build environment (64-bit)... >>> bash: >>> /home/sdr-dev/xilinx/Vivado_HLS/2015.2/.settings64-Vivado_High_Level_Synthesis.sh: >>> No such file or directory >>> bash: /opt/Xilinx/DocNav/.settings64-DocNav.sh: No such file or directory >>> - Vivado: Found (/home/sdr-dev/xilinx/Vivado/2015.2/bin) >>> >>> Environment successfully initialized. >>> >>> >>> >>> I then run the command >>> >>> make X310_RFNOC_HGS >>> >>> yielding a message saying >>> >>> >>> INFO: [Common 17-206] Exiting Webtalk at Mon Apr 25 14:31:25 2016... >>> INFO: [Vivado 12-3441] generate_netlist_ip - operation complete >>> synth_ip: Time (s): cpu = 00:00:58 ; elapsed = 00:01:17 . Memory (MB): >>> peak = 1857.766 ; gain = 970.414 ; free physical = 4787 ; free virtual = >>> 14137 >>> # if [string match $gen_example_proj "1"] { >>> # puts "BUILDER: Generating Example Design..." >>> # open_example_project -force -dir . [get_ips $ip_name] >>> # } >>> BUILDER: Generating Example Design... >>> ERROR: [Common 17-69] Command failed: * The IP Data in the repository is >>> incompatible with the current instance (despite having identical Version >>> and Revision). You will need to update the IP before viewing the >>> customization and generating outputs. >>> * IP file >>> '/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xml' >>> for IP 'ten_gig_eth_pcs_pma' contains stale content. >>> Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl >>> command 'report_ip_status' for more information. >>> INFO: [Common 17-206] Exiting Vivado at Mon Apr 25 14:31:25 2016... >>> Releasing IP location: >>> /home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma >>> make[1]: *** >>> [/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/ten_gig_eth_pcs_pma/ten_gig_eth_pcs_pma.xci.out] >>> Error 1 >>> make[1]: Leaving directory >>> `/home/sdr-dev/repo/uhd/fpga-src/usrp3/top/x300' >>> make: *** [X310_RFNOC_HGS] Error 2 >>> >>> >>> >>> >>> >>> On Sun, Apr 10, 2016 at 12:52 PM, Jonathon Pendlum via USRP-users < >>> usrp-users@lists.ettus.com> wrote: >>> >>>> Hi Patrick, >>>> >>>> What branch are you on? rfnoc-devel or rfnoc-ofdm? Did you run source >>>> setupenv.sh in the usrp3/top/x300/ directory? What is it output? >>>> >>>> >>>> >>>> Jonathon >>>> >>>> _______________________________________________ >>>> USRP-users mailing list >>>> USRP-users@lists.ettus.com >>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>> >>>> >>> >> >