Empathy List Archives

AK

Attila Kinali

Sat, Jul 7, 2018 7:21 PM

Moin,

For a project I am doing, I need a high resolution, high linearity ADC.
As it does not need to be fast, I choose to build a multi-slope ADC
à la <insert your favorite DMM>. The basic circuit I came up with is attached.

The LTC2380-24 is good for about 1µV at a +/-5V range (including noise
and INL). The two LT6018 infront of it give it a gain of 8.8 and the
integrator has a gain of 50 per ms of integration time. Input range is +/-10V.

Unless I am missing something, the noise of the whole system is dominated
by the input noise of the integrator, namely the 20k resistor that gives
a noise voltage density of ~18nV/√Hz, plus the 250nVpp low frequency
noise of the ADA4077

Assuming we use a 100ms integration time, we get an input related
resolution of 22pV. The input resistor noise over a bandwidth of 10Hz
is 57nVrms. The low frequency noise of the AD4077 is 250nVpp/3=83nVrms.
So the total noise ends up being 100nVrms or 300nVpp. Which is
about 7.8 digits or 25.9bits ENOB.

If we go to 1s integration time, the noise changes to 18nVrms and 177Vpp, respectively. Added together this becomes 62nVrms or 185nVpp. Which in turn
is 8 digits or 26.7bits ENOB.

Now to the questions :-)

Is my assumption correct, that the integrator dominates the noise
in this system?
If I look at the documentation of the HP3458, they reach 28bits at
166ms integration time. Yet the HP Journal article talks about 100nV/√Hz
input noise. Ie the noise of the HP3458 is over a factor 5 higher, yet the
ENOB @100ms is 2 bits better. It barely matches up, when I ignore the
low frequency noise, but the factor of 5 in noise (or 2.3 bits) difference
remains. Where does this discrepancy come from?
```
 	Attila Kinali
```

--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

Moin, For a project I am doing, I need a high resolution, high linearity ADC. As it does not need to be fast, I choose to build a multi-slope ADC à la <insert your favorite DMM>. The basic circuit I came up with is attached. The LTC2380-24 is good for about 1µV at a +/-5V range (including noise and INL). The two LT6018 infront of it give it a gain of 8.8 and the integrator has a gain of 50 per ms of integration time. Input range is +/-10V. Unless I am missing something, the noise of the whole system is dominated by the input noise of the integrator, namely the 20k resistor that gives a noise voltage density of ~18nV/√Hz, plus the 250nVpp low frequency noise of the ADA4077 Assuming we use a 100ms integration time, we get an input related resolution of 22pV. The input resistor noise over a bandwidth of 10Hz is 57nVrms. The low frequency noise of the AD4077 is 250nVpp/3=83nVrms. So the total noise ends up being 100nVrms or 300nVpp. Which is about 7.8 digits or 25.9bits ENOB. If we go to 1s integration time, the noise changes to 18nVrms and 177Vpp, respectively. Added together this becomes 62nVrms or 185nVpp. Which in turn is 8 digits or 26.7bits ENOB. Now to the questions :-) 1) Is my assumption correct, that the integrator dominates the noise in this system? 2) If I look at the documentation of the HP3458, they reach 28bits at 166ms integration time. Yet the HP Journal article talks about 100nV/√Hz input noise. Ie the noise of the HP3458 is over a factor 5 higher, yet the ENOB @100ms is 2 bits better. It barely matches up, when I ignore the low frequency noise, but the factor of 5 in noise (or 2.3 bits) difference remains. Where does this discrepancy come from? Attila Kinali -- <JaberWorky> The bad part of Zurich is where the degenerates throw DARK chocolate at you.

PK

Poul-Henning Kamp

Sat, Jul 7, 2018 7:51 PM

In message 20180707212145.82f74e719b3854ca9cff0485@kinali.ch, Attila Kinali writes:

If I look at the documentation of the HP3458, they reach 28bits at
166ms integration time. Yet the HP Journal article talks about 100nV/√Hz
input noise. Ie the noise of the HP3458 is over a factor 5 higher, yet the
ENOB @100ms is 2 bits better. It barely matches up, when I ignore the
low frequency noise, but the factor of 5 in noise (or 2.3 bits) difference
remains. Where does this discrepancy come from?

I am not sure why you call your circuit a "multi-slope ADC", I can
only see one pair of current sources ?

HP3458 uses six different slopes (Fig 8/p. 12) in a deviously
smart asymmetric layout: [+1024,+256,+16,+1,-4,-64,-256,-1024]

The trick to multislope is that it can cut down the convergence
time, and that in turn reduces the effect of all the drift/leakage
error sources proportionally.

I suspect you also significantly underestimate the "non-ideal
component" source of errors.

The trick in Fig 7/p.12 is much more important than most people
realize and HP's implementation is significantly more interesting
than Fig 7 lets on, because it involves 8 switches instead of two.

If you want to have any dream of getting performance like HP3458,
you will have to write a lot of code to do the same "auto"-calibrations
as the HP3458, and you will have to run it on a regular basis to
cope with component drift.

There is no free lunches after bit 20...

--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

-------- In message <20180707212145.82f74e719b3854ca9cff0485@kinali.ch>, Attila Kinali writes: >2) If I look at the documentation of the HP3458, they reach 28bits at >166ms integration time. Yet the HP Journal article talks about 100nV/√Hz >input noise. Ie the noise of the HP3458 is over a factor 5 higher, yet the >ENOB @100ms is 2 bits better. It barely matches up, when I ignore the >low frequency noise, but the factor of 5 in noise (or 2.3 bits) difference >remains. Where does this discrepancy come from? I am not sure why you call your circuit a "multi-slope ADC", I can only see one pair of current sources ? HP3458 uses six different slopes (Fig 8/p. 12) in a deviously smart asymmetric layout: [+1024,+256,+16,+1,-4,-64,-256,-1024] The trick to multislope is that it can cut down the convergence time, and that in turn reduces the effect of all the drift/leakage error sources proportionally. I suspect you also significantly underestimate the "non-ideal component" source of errors. The trick in Fig 7/p.12 is much more important than most people realize and HP's implementation is significantly more interesting than Fig 7 lets on, because it involves 8 switches instead of two. If you want to have any dream of getting performance like HP3458, you will have to write a lot of code to do the same "auto"-calibrations as the HP3458, and you will have to run it on a regular basis to cope with component drift. There is no free lunches after bit 20... -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 phk@FreeBSD.ORG | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence.

AK

Attila Kinali

Sat, Jul 7, 2018 8:35 PM

Hoi Poul-Henning!

On Sat, 07 Jul 2018 19:51:36 +0000
"Poul-Henning Kamp" phk@phk.freebsd.dk wrote:

I am not sure why you call your circuit a "multi-slope ADC", I can
only see one pair of current sources ?

Ah..sorry.. because of the multi-slope run-up. In the setup I have
there is no need for the run-down due to the high resolution ADC
following the integrator. Sorry, I should have been more clear
about this.

The trick to multislope is that it can cut down the convergence
time, and that in turn reduces the effect of all the drift/leakage
error sources proportionally.

The run-down is cut away completely. The LTC2380-24 takes about 1024
samples to get down to <2LSB rms error, which takes approximately 0.5ms.
I do not think that any multi-slope run-down would get to this precision
this quickly.

I suspect you also significantly underestimate the "non-ideal
component" source of errors.

Very likely. Though the main one that I could not properly quantify
yet are the charge injections from the switches, because....

The trick in Fig 7/p.12 is much more important than most people
realize and HP's implementation is significantly more interesting
than Fig 7 lets on, because it involves 8 switches instead of two.

... I don't know how well the keep-the-number-of-switch-operations-constant
trick cancels things out. For the moment I assume that they do perfectly
cancel out to the point that the system is noise limited. The behaviour
of the switches is also the reason why I use current sources instead of
resistors and reference voltages. This way, the current sources eliminate
the error due to change of resistance through the switches. Unfortunately,
they add another error due to the jump of the current during the switch
operation. I have not yet spend enough time to quantify this error to
say anything about its magnitude.

Another source of non-ideality that I was unable to quantify so far
is the dielectric absorption of the integration capacitor. I hope that
the idea of keeping its voltage below 1V should help keeping this problem
at bay. Especially considering that the HP3458 gets away with a simple
MLCC ceramic capacitor (SA10 series 330pF from AVX) and a small compensation
circuit with a tau of 24µs (100pF+243R).

If you want to have any dream of getting performance like HP3458,
you will have to write a lot of code to do the same "auto"-calibrations
as the HP3458, and you will have to run it on a regular basis to
cope with component drift.

Yes. The idea is that the ADC runs a cycle offset+gain calibration,
7 measurements, calibration, 7 measurements,... etc pp which should
result in a cycle time of slighly less than 2s. My assumption is that
the drift of components is low enough that they change insignificantly
within those 2s. To keep the calibration measurments short is the reason
why ther are only a single positive and negative current source, and not
multiple as the HP3458 does.

There is no free lunches after bit 20...

Oh yes... That design is the results of many weeks of reading up on
how ADCs work and how to get them accurate and precise.

		Attila Kinali

--
<JaberWorky> The bad part of Zurich is where the degenerates
throw DARK chocolate at you.

Hoi Poul-Henning! On Sat, 07 Jul 2018 19:51:36 +0000 "Poul-Henning Kamp" <phk@phk.freebsd.dk> wrote: > I am not sure why you call your circuit a "multi-slope ADC", I can > only see one pair of current sources ? Ah..sorry.. because of the multi-slope run-up. In the setup I have there is no need for the run-down due to the high resolution ADC following the integrator. Sorry, I should have been more clear about this. > The trick to multislope is that it can cut down the convergence > time, and that in turn reduces the effect of all the drift/leakage > error sources proportionally. The run-down is cut away completely. The LTC2380-24 takes about 1024 samples to get down to <2LSB rms error, which takes approximately 0.5ms. I do not think that any multi-slope run-down would get to this precision this quickly. > I suspect you also significantly underestimate the "non-ideal > component" source of errors. Very likely. Though the main one that I could not properly quantify yet are the charge injections from the switches, because.... > The trick in Fig 7/p.12 is much more important than most people > realize and HP's implementation is significantly more interesting > than Fig 7 lets on, because it involves 8 switches instead of two. ... I don't know how well the keep-the-number-of-switch-operations-constant trick cancels things out. For the moment I assume that they do perfectly cancel out to the point that the system is noise limited. The behaviour of the switches is also the reason why I use current sources instead of resistors and reference voltages. This way, the current sources eliminate the error due to change of resistance through the switches. Unfortunately, they add another error due to the jump of the current during the switch operation. I have not yet spend enough time to quantify this error to say anything about its magnitude. Another source of non-ideality that I was unable to quantify so far is the dielectric absorption of the integration capacitor. I hope that the idea of keeping its voltage below 1V should help keeping this problem at bay. Especially considering that the HP3458 gets away with a simple MLCC ceramic capacitor (SA10 series 330pF from AVX) and a small compensation circuit with a tau of 24µs (100pF+243R). > If you want to have any dream of getting performance like HP3458, > you will have to write a lot of code to do the same "auto"-calibrations > as the HP3458, and you will have to run it on a regular basis to > cope with component drift. Yes. The idea is that the ADC runs a cycle offset+gain calibration, 7 measurements, calibration, 7 measurements,... etc pp which should result in a cycle time of slighly less than 2s. My assumption is that the drift of components is low enough that they change insignificantly within those 2s. To keep the calibration measurments short is the reason why ther are only a single positive and negative current source, and not multiple as the HP3458 does. > There is no free lunches after bit 20... Oh yes... That design is the results of many weeks of reading up on how ADCs work and how to get them accurate and precise. Attila Kinali -- <JaberWorky> The bad part of Zurich is where the degenerates throw DARK chocolate at you.

PK

Poul-Henning Kamp

Sat, Jul 7, 2018 10:15 PM

In message 20180707223550.9b8895259ab8a8441b9bc04d@kinali.ch, Attila Kinali writes:

I just want to say up front that all the stuff I'm dragging
up here is in no way meant to discourage you from trying,
but rather to give you ideas what to look out for.

For reasons of computer-archeology I spent a lot of time with the
HP3458A firmware and anybody who thinks the hardware is 50% of the
magic in the HP3458A is badly underestimating the software.

The trick to multislope is that it can cut down the convergence
time, and that in turn reduces the effect of all the drift/leakage
error sources proportionally.

The run-down is cut away completely. The LTC2380-24 takes about 1024
samples to get down to <2LSB rms error, which takes approximately 0.5ms.
I do not think that any multi-slope run-down would get to this precision
this quickly.

I'm not entirely convinced the LTC2380 will either, unless your
input signal has just the right amount of thermal noise.

The trick in Fig 7/p.12 is much more important than most people
realize and HP's implementation is significantly more interesting
than Fig 7 lets on, because it involves 8 switches instead of two.

... I don't know how well the keep-the-number-of-switch-operations-constant
trick cancels things out. For the moment I assume that they do perfectly
cancel out to the point that the system is noise limited.

After calibration, they cancel out as perfect as you can calibrate
them. This is one of the reasons why HP "reserve" some bits
of their theoretical resolution: They expend them in autocal.

The behaviour
of the switches is also the reason why I use current sources instead of
resistors and reference voltages.

Current sources contain feedback loops and therefore react
(nonlinearly?) to the switch being operated. I don't think calibrating
that out is feasible (enough.)

You will have to autocal the full "ADSR" (see: "Moog") of the the
switches no matter what you do, so trying to use temporally
nonlinear current sources to compensate for the 'S' part seems pointless.

Resistors and reference voltages are much simpler to model
and calibrate.

Especially considering that the HP3458 gets away with a simple
MLCC ceramic capacitor (SA10 series 330pF from AVX) and a small compensation
circuit with a tau of 24µs (100pF+243R).

They also calibrate that in software, and I seem to recall that
they have some screwy math involving temperature in that code.

You will need to do something like that too, but you can probably
approximate a polynomia over time, given enough data.

Yes. The idea is that the ADC runs a cycle offset+gain calibration,
7 measurements, calibration, 7 measurements,... etc pp which should
result in a cycle time of slighly less than 2s.

That's certainly feasible, but far from enough.

You will need to periodically do most of the steps in the 10V section
of the HP3458A's "ACAL DCV" which takes 16 seconds for good reasons.

How often you will need to do that "big autocal" is probably largely
a matter of components and pratical construction.

It may be well worth your time to pick through 1000 random integration
capacitors to find the best one, but don't bother buying a batch
of 1000 sequentially produced capacitors, modern quality control
is far too good for that to work.

And you probably have to mount all of it dead-bug style to keep the
parasitics down and carefully balance the number of thermocouples.

Poul-Henning

--
Poul-Henning Kamp | UNIX since Zilog Zeus 3.20
phk@FreeBSD.ORG | TCP/IP since RFC 956
FreeBSD committer | BSD since 4.3-tahoe
Never attribute to malice what can adequately be explained by incompetence.

-------- In message <20180707223550.9b8895259ab8a8441b9bc04d@kinali.ch>, Attila Kinali writes: I just want to say up front that all the stuff I'm dragging up here is in no way meant to discourage you from trying, but rather to give you ideas what to look out for. For reasons of computer-archeology I spent a lot of time with the HP3458A firmware and anybody who thinks the hardware is 50% of the magic in the HP3458A is badly underestimating the software. >> The trick to multislope is that it can cut down the convergence >> time, and that in turn reduces the effect of all the drift/leakage >> error sources proportionally. > >The run-down is cut away completely. The LTC2380-24 takes about 1024 >samples to get down to <2LSB rms error, which takes approximately 0.5ms. >I do not think that any multi-slope run-down would get to this precision >this quickly. I'm not entirely convinced the LTC2380 will either, unless your input signal has just the right amount of thermal noise. >> The trick in Fig 7/p.12 is much more important than most people >> realize and HP's implementation is significantly more interesting >> than Fig 7 lets on, because it involves 8 switches instead of two. > >... I don't know how well the keep-the-number-of-switch-operations-constant >trick cancels things out. For the moment I assume that they do perfectly >cancel out to the point that the system is noise limited. After calibration, they cancel out as perfect as you can calibrate them. This is one of the reasons why HP "reserve" some bits of their theoretical resolution: They expend them in autocal. >The behaviour >of the switches is also the reason why I use current sources instead of >resistors and reference voltages. Current sources contain feedback loops and therefore react (nonlinearly?) to the switch being operated. I don't think calibrating that out is feasible (enough.) You will have to autocal the full "ADSR" (see: "Moog") of the the switches no matter what you do, so trying to use temporally nonlinear current sources to compensate for the 'S' part seems pointless. Resistors and reference voltages are much simpler to model and calibrate. >Especially considering that the HP3458 gets away with a simple >MLCC ceramic capacitor (SA10 series 330pF from AVX) and a small compensation >circuit with a tau of 24µs (100pF+243R). They also calibrate that in software, and I seem to recall that they have some screwy math involving temperature in that code. You will need to do something like that too, but you can probably approximate a polynomia over time, given enough data. >Yes. The idea is that the ADC runs a cycle offset+gain calibration, >7 measurements, calibration, 7 measurements,... etc pp which should >result in a cycle time of slighly less than 2s. That's certainly feasible, but far from enough. You will need to periodically do most of the steps in the 10V section of the HP3458A's "ACAL DCV" which takes 16 seconds for good reasons. How often you will need to do that "big autocal" is probably largely a matter of components and pratical construction. It may be well worth your time to pick through 1000 random integration capacitors to find the best one, but don't bother buying a batch of 1000 sequentially produced capacitors, modern quality control is far too good for that to work. And you probably have to mount all of it dead-bug style to keep the parasitics down and carefully balance the number of thermocouples. Poul-Henning -- Poul-Henning Kamp | UNIX since Zilog Zeus 3.20 phk@FreeBSD.ORG | TCP/IP since RFC 956 FreeBSD committer | BSD since 4.3-tahoe Never attribute to malice what can adequately be explained by incompetence.

BG

Bruce Griffiths

Sat, Jul 7, 2018 10:42 PM

You are likely to need a more complex integrator than one using a single opamp to achieve adequate linearity. The 3458A used 3 opamps, the 34401a used 2 opamps in their integrators.
To minimise the effect of dielectric absorption an integrator control loop that maintains low average, ideally zero, (not just within low upper and lower bounds) output voltage is likely necessary. Also the the Ron of the switches can be compensated by ensuring that the output Resistance of the signal "current source" matches that of the ramp current sources. Simplest solution is to set the output resistance of all to 20k.

Bruce

On 08 July 2018 at 08:35 Attila Kinali attila@kinali.ch wrote: