Best way for generating 8994.03 MHz from 2899.00042272.....MHz?
Dear nuts,
A colleague from a Free Electron Laser lab has the following problem:
he needs to make a frequency to use as an X-band LO that is
exactly8994.03 MHz (32998.01 MHz) and it
must be locked to his S-band LO which is exactly 2998.01732/757 MHz
(2899.00042272.....MHz). He intends to multiply his S-LO by 3 and that gets
him close, about 297 MHz away. Then he can add another frequency he has(that
is locked to his S-LO) of 241.6..... MHz (2998.01*61/757 MHz to be exact)
and that brings him to about 55 MHz. To generate that 55 MHz he has several
options:
- Cascading two DDS chips to get many bits of frequency resolution and leave
the thing in open loop. I don't like the absence of feedback in this option,
and I have never cascaded DDS chips to achieve an increase in frequency
resolution, although on paper there seems to be no problem. The increase in
accuracy would be such that even in open loop it would take a very very long
time to go out of spec (his spec is 0.01 degrees at X-band, during a whole
year). This time would be long enough for him not to care about it. - Generating it using a standard PLL with some kind of good quality VCO. He
is concerned by the required VCO quality in this case. - Combining the two above, i.e. using the DDS as a VCO by controlling its
Frequency Tuning Word, but in a closed loop configuration.
Has anybody out there been confronted to a similar problem? Many thanks in
advance,
Javier
so there is one frequency that is X*(732/757), and he want to get X*3
from this? Seems like an integer-N PLL could do this pretty
straightforwardly, although I'd have to spend some time to figure out
the exact multiples. National Semiconductor has an app note on
frequency planning for synthsizers that would cover this.
Dave
On Fri, Aug 14, 2009 at 1:39 PM, Javier
Serranojavier.serrano.pareja@gmail.com wrote:
Dear nuts,
A colleague from a Free Electron Laser lab has the following problem:
he needs to make a frequency to use as an X-band LO that is
exactly8994.03 MHz (32998.01 MHz) and it
must be locked to his S-band LO which is exactly 2998.01732/757 MHz
(2899.00042272.....MHz). He intends to multiply his S-LO by 3 and that gets
him close, about 297 MHz away. Then he can add another frequency he has(that
is locked to his S-LO) of 241.6..... MHz (2998.01*61/757 MHz to be exact)
and that brings him to about 55 MHz. To generate that 55 MHz he has several
options:
- Cascading two DDS chips to get many bits of frequency resolution and leave
the thing in open loop. I don't like the absence of feedback in this option,
and I have never cascaded DDS chips to achieve an increase in frequency
resolution, although on paper there seems to be no problem. The increase in
accuracy would be such that even in open loop it would take a very very long
time to go out of spec (his spec is 0.01 degrees at X-band, during a whole
year). This time would be long enough for him not to care about it. - Generating it using a standard PLL with some kind of good quality VCO. He
is concerned by the required VCO quality in this case. - Combining the two above, i.e. using the DDS as a VCO by controlling its
Frequency Tuning Word, but in a closed loop configuration.
Has anybody out there been confronted to a similar problem? Many thanks in
advance,
Javier
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David Bengtson wrote:
so there is one frequency that is X*(732/757), and he want to get X*3
from this? Seems like an integer-N PLL could do this pretty
straightforwardly, although I'd have to spend some time to figure out
the exact multiples. National Semiconductor has an app note on
frequency planning for synthsizers that would cover this.
Dave
Yes. The ideal architecture would be to use a dielectric resonator
oscillator at 8994 MHz as the output source. Then divide its output by
two. Take that ~4.5 GHz signal and divide it by 757 using the divide by N
section of an Analog Devices ADF4106. Divide the 2998 MHz by 486
using the divide by N section of a second ADF4106. 486 is 2/3 of
732.
Feed the "muxout" of the second ADF4108 into the "ref in" of the first
ADF4108 and use the phase detector in the first ADF4108 to tune the DRO.
(This will become clear after you read the ADF4108 data sheet :-) The
phase detector frequency will be about 5 MHz.
Rick Karlquist N6RK
Corrected version:
Yes. The ideal architecture would be to use a dielectric resonator
oscillator at 8994 MHz as the output source. Then divide its output by
two. Take that ~4.5 GHz signal and divide it by 757 using the divide by N
section of an Analog Devices ADF4106. Divide the 2899 MHz by
488 using the divide by N section of a second ADF4106. 488 is 2/3 of
732.
Feed the "muxout" of the second ADF4106 into the "ref in" of the first
ADF4108 and use the phase detector in the first ADF4106 to tune the DRO.
(This will become clear after you read the ADF4106 data sheet :-) The
phase detector frequency will be about 6 MHz.
Rick Karlquist N6RK
These days, you might want to consider using the GaAs VCOs from Hittite,
rather than the DRO. DROs are SUCH a pain to build and tune, being a
mechanical resonator in a cavity. Everything you do seems to adversely
affect the DRO. The MMIC VCO is just a die (or a die in a package) and it's
pretty much immune to external effects, since the resonator is built into
the oscillator.
We built some prototypes at JPL using the VCO and a GaAs divider, and the
performance was better than DROs.
If you were building a very narrow band PLL, where tunability of the DRO
isn't needed over a wide range, the DRO might be a good solution, but still,
you have microphonics, etc. (we used to demonstrate the latter by hooking up
the output to a spectrum analyzer that has a FM demodulator, and talking to
the DRO)
On 8/14/09 5:53 PM, "Rick Karlquist" richard@karlquist.com wrote:
David Bengtson wrote:
so there is one frequency that is X*(732/757), and he want to get X*3
from this? Seems like an integer-N PLL could do this pretty
straightforwardly, although I'd have to spend some time to figure out
the exact multiples. National Semiconductor has an app note on
frequency planning for synthsizers that would cover this.
Dave
Yes. The ideal architecture would be to use a dielectric resonator
oscillator at 8994 MHz as the output source. Then divide its output by
two. Take that ~4.5 GHz signal and divide it by 757 using the divide by N
section of an Analog Devices ADF4106. Divide the 2998 MHz by 486
using the divide by N section of a second ADF4106. 486 is 2/3 of
732.
Feed the "muxout" of the second ADF4108 into the "ref in" of the first
ADF4108 and use the phase detector in the first ADF4108 to tune the DRO.
(This will become clear after you read the ADF4108 data sheet :-) The
phase detector frequency will be about 5 MHz.
Rick Karlquist N6RK
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To unsubscribe, go to https://www.febo.com/cgi-bin/mailman/listinfo/time-nuts
and follow the instructions there.
Lux, Jim (337C) wrote:
These days, you might want to consider using the GaAs VCOs from Hittite,
rather than the DRO. DROs are SUCH a pain to build and tune, being a
mechanical resonator in a cavity. Everything you do seems to adversely
affect the DRO. The MMIC VCO is just a die (or a die in a package) and
it's
pretty much immune to external effects, since the resonator is built into
the oscillator.
We built some prototypes at JPL using the VCO and a GaAs divider, and the
performance was better than DROs.
If you were building a very narrow band PLL, where tunability of the DRO
isn't needed over a wide range, the DRO might be a good solution, but
still,
you have microphonics, etc. (we used to demonstrate the latter by hooking
up
the output to a spectrum analyzer that has a FM demodulator, and talking
to
the DRO)
We've used both. The DRO has much better open loop phase noise, and this
synthesizer is for a single frequency, so the DRO only needs enough
tuning to make up for drift. I was assuming the original poster
would purchase a DRO. I agree that they are not something you
want to build. We had no trouble with the ones we purchased
from various vendors. BTW, the 5071A cesium frequency standard
uses a DRO to help generate the 9192... MHz signal that
excites the CBT, as explained in my FCS paper in the early
90's.
I don't understand how you got worse phase noise with a DRO
than a VCO, unless you used a narrow loop bandwidth for the
DRO and a wide loop bandwidth for the VCO. We try to get the
loop bandwidth up around 1 MHz for DRO's. The wide bandwidth
also mitigates against microphonics. One thing we found was
that you want to cover up the tuning screw hole so that microwaves
don't go out of the hole and bounce around and go back inside.
We had to put copper tape over it.
Perhaps the original poster should start with a VCO and see
if the phase noise is good enough, then go to a DRO if necessary.
Rick Karlquist N6RK
On 8/14/09 7:17 PM, "Rick Karlquist" richard@karlquist.com wrote:
Lux, Jim (337C) wrote:
These days, you might want to consider using the GaAs VCOs from Hittite,
rather than the DRO. DROs are SUCH a pain to build and tune, being a
mechanical resonator in a cavity. Everything you do seems to adversely
affect the DRO. The MMIC VCO is just a die (or a die in a package) and
it's
pretty much immune to external effects, since the resonator is built into
the oscillator.
We've used both. The DRO has much better open loop phase noise, and this
synthesizer is for a single frequency, so the DRO only needs enough
tuning to make up for drift. I was assuming the original poster
would purchase a DRO. I agree that they are not something you
want to build. We had no trouble with the ones we purchased
from various vendors. BTW, the 5071A cesium frequency standard
uses a DRO to help generate the 9192... MHz signal that
excites the CBT, as explained in my FCS paper in the early
90's.
I don't understand how you got worse phase noise with a DRO
than a VCO, unless you used a narrow loop bandwidth for the
DRO and a wide loop bandwidth for the VCO.
Same basic loop for both.. (well, adjusted so the in-loop noise blends into
the outside the loop noise..but the turnover was pretty similar)
http://tmo.jpl.nasa.gov/progress_report/42-166/166A.pdf is probably the only
published data readily available.
Perhaps the original poster should start with a VCO and see
if the phase noise is good enough, then go to a DRO if necessary.
Sure is easier with the MMIC.