Yes, please consider it. I would be very interested in the results.

We measured under 2 ps jitter for the PIC dividers [1] used with the cute little TADD-2 board [2]. One of these days I should measure your divider board with the same setup to see how it compares with a PIC. Like a CPLD/FPGA the PIC has the advantage of being fully synchronous and all on one die.

/tvb

[1] http://leapsecond.com/pic/
[2] https://www.tapr.org/kits_t2-mini.html

Programmable logic rocks. If you need a 13 bit counter, you can do that. It
is easy to create alarms and special controls.

Jerry
On Jun 2, 2015 2:22 PM, "David C. Partridge" david.partridge@perdrix.co.uk
wrote:

Am 02.06.2015 um 21:27 schrieb Tom Van Baak:

I have made a stamp sized board that has a Xilinx 2C64 Coolrunner II, a
1.8V regulator for the core
voltage and the programming interface for the standard Xilinx USB-cable.
(parallel cable may work
but my laptop has no parallel port anymore.) It runs on 3.3V. All I/O pads
are fanned out to a 100 mil grid, so you can mount it easily on square
pad board or solder it to an
unetched copper clad board. The layout is single sided plus unbroken GND
on the bottom side.

pic = <
https://picasaweb.google.com/lh/photo/4Bpcfouj8WH0shNGIyuVUtMTjNZETYmyPJy0liipFm0?feat=directlink

(top right)

The CPLD has 64 Flipflops and enough combinational logic to feed them
all. It runs happily
at > 200 MHZ. Two of these chips can make a 1pps from 200 MHz in, and
another 1pps that
can be stepped in 5ns increments from -100nsec to > +1 second. A 2c64
costs $2 or so at digikey.

BTW, the other stamps on the picture are:

top left:  Crystec CVH950 100 MHz VCXO locked to 10 MHz. I was too slow
with those 100 MHz Wenzels this week;
these would have justified a better effort; also sth.
better than an 4046 ;-)

bottom left: NIST doubler from 100 MHz to 200 MHz using 2*BF862, slight
gain, Low-Q tuned circuit
on the output side

bottom right: 200 MHz to 400 MHz Schottky doubler, SAW filter, ERA-4 to
bring it to 12 dBm again

The boards are home-etched; because of my daytime job my pps generator
makes only slow progress...

A 1:1 pdf of the layout is available; one can print it to foil if one
has a good printer (OKI 852 works
nicely) or a print shop that can do offset films will print it to
document film for €5 to 10 per ISO A4 page+

If someone want to measure it, I can send him one of those Xilinx
stamps; sooner or later I'll find
the time do it myself but even then the repeatability would be interesting.

Also, this morning I have published an update for my 220pV/sqrt Hz
preamplifier; 10uF foil
capacitors one actually can buy, circuit diagrams and Gerbers for the
adventurous. Be warned,
this version has never been fabricated, but the changes from its
predecessor are relatively small. Most of
the work was the step to Altium Designer 15, Direct-X support on my
virtual Win7 machine and that my
libraries from Protel-99 times desparately need some work.

The update can be found at  <
http://www.hoffmann-hochfrequenz.de/downloads/downloads.html >.

regards, Gerhard

Hi

A lot depends on exactly which CPLD or which FPGA you are looking at and how
they put the guts of it together. If you find one that is “just right” it might be within
10 db of high speed CMOS. Since there is a 20 db delta between the HC you mention
and the AC that leaves a bit of room.

If you have a part with a bias generator in it, just forget about using it. You will have all
sorts of strange spurs that come and go. They will be broadband. They will take the
noise floor up into the 100 dbc / Hz range in some cases.

If you are trying to use the internal PLL, it’s phase noise isn’t going to be great. Numbers
like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output.

As straight dividers, they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz
you could expect under similar conditions with something like AC or faster CMOS. You
are more likely to get there on a fast CLPD than on an FPGA. Either way you can run
into bum parts.

Bob

On Tue, 2 Jun 2015 14:13:04 +0100
"David C. Partridge" david.partridge@perdrix.co.uk wrote:

It depends ;-)

For most things it should be ok. You can reach lower levels of noise
with single 74xxx parts as you will have lower interference between
different parts of the circuitry. But how much better it might be
and whether other effects might actually make the "discrete" solution
worse, i cannot say.

For some rule of thumb guide lines, the poster/paper by Caloso
which he presented at EFTF last year where they measured noise
parameters of 4 different FPGA families. The main result is that
"the larger the better" is also true for low noise logic gates,
but there are outliers.

"Phase noise jitter in digital electronics", by Calosso and Rubiola, 2014
http://rubiola.org/pdf-articles/conference/2014-eftf-Noise-in-digital-components.pdf

There is quite some data missing there, but I guess they hit the
page limit of the paper. Also testing different FPGA families would
be quite nice.

		Attila Kinali

--
< av500> phd is easy
< av500> getting dsl is hard

On Tuesday, June 02, 2015 02:13:04 PM David C. Partridge wrote:

`

It makes it easier to implement low noise lambda dividers which overcome
most of the PN degradation of digital dividers.
Also the FPGA can easily be reconfigured to produce outputs different from
those originally implemented.

Bruce

You can always cleanup the outputs of the CPLD or FPGA by resynchronising the outputs to the input clock using a dedicated D flipflop for each output.

Bruce

 On Wednesday, 3 June 2015 3:22 PM, Bob Camp <kb8tq@n1k.org> wrote:

Hi

A lot depends on exactly which CPLD or which FPGA you are looking at and how
they put the guts of it together. If you find one that is “just right” it might be within
10 db of high speed CMOS. Since there is a 20 db delta between the HC you mention
and the AC that leaves a bit of room.

If you have a part with a bias generator in it, just forget about using it. You will have all
sorts of strange spurs that come and go. They will be broadband. They will take the
noise floor up into the 100 dbc / Hz range in some cases.

If you are trying to use the internal PLL, it’s phase noise isn’t going to be great. Numbers
like -135 dbc / Hz at 100 KHz offset are not uncommon on an HF output.

As straight dividers, they might get to -16x dbc/ Hz region. That compares to the -174 dbc / Hz
you could expect under similar conditions with something like AC or faster CMOS. You
are more likely to get there on a fast CLPD than on an FPGA. Either way you can run
into bum parts.

Bob

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Hi

As always, the real answer it “that depends”.

If your objective is wide band phase noise and you want to start from 100 MHz and get 10 MHz (fig 6 in
the Lamda paper), you can get at least another 6 db with a simple divide by 10 chip than with all the
fancy stuff.

Bob

Thanks Bruce.  That is an excellent option.

I did a paper over a decade ago on the jitter and phase noise for Actel
(Now Microsemi) comparing their eX device to the Xilinx CPLD.  It was
intended to show the eX device was preferable to the Xilinx CPLD.  It makes
a difference as to what device is selected.

Jerry

On Tue, Jun 2, 2015 at 11:17 PM, Bruce Griffiths <bruce.griffiths@xtra.co.nz