Am 08.11.2014 um 18:21 schrieb Robert Darby:

Probably yes, but I have never used the XC95 family.

The Coolrunners use very little power, can do > 250 MHz
and store their own configuration. Wierd enough, their
Flipflops can switch on both the rising AND the falling edge.

I have revitalized my HiLO All-11 programmer from the
times when PALs/GALS and Eproms were great. Its
software now runs in a virtual XP machine under Linux Mint /
VMware with an USB to serial cable made by HAMA.

Gerhard

BTW, this is the 10/100MHz --> 1pps-generator in the 2C64:
(I have removed some debug outputs, hopefully I did not mess it up)

-- Company:        Hoffmann RF & DSP
-- Create Date:    09:09:37 08/08/2012
-- Module Name:    pps1_generator - Behavioral
-- Target Devices:  X2c64A-5VQ44
-- Additional Comments:  Free firmware under BSD license

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity pps1_generator is
Port(
clk        : in  STD_LOGIC;
RunAt100MHz : in  STD_LOGIC;
pps1_out    : out STD_LOGIC
);
end pps1_generator;

architecture Behavioral of pps1_generator is
signal tctr      : integer range 0 to 99999999;
signal pw_ctr    : integer range 0 to 199999;
signal cycle_done : boolean;
signal pw_done    : boolean;

 function bool2sl(b : boolean) return std_logic is
 begin
     if b then
         return '1';
     else
         return '0';
     end if;
 end function bool2sl;

begin

 u_div : process(clk) is
 begin
     if rising_edge(clk) then
         cycle_done <= (tctr = 0); -- pipeline the comparator

         if cycle_done
         then
             if RunAt100MHz = '1' then
                 tctr <= 100000000 - 2; -- divide by 100 Meg
             else
                 tctr <= 10000000 - 2; -- divide by 10 Meg
             end if;

         else
             tctr <= tctr - 1;
         end if;

     end if;                         -- rising_edge()
 end process u_div;

-- produce the standard 20 usec pulsewidth
u_pulsewidth : process(clk) is
begin
if rising_edge(clk) then
if cycle_done then
if RunAt100MHz = '1' then
pw_ctr <= 1999;
else
pw_ctr <= 199;
end if;

         elsif pw_ctr /= 0 then
             pw_ctr <= pw_ctr - 1;
         end if;

         pps1_out <= bool2sl(pw_ctr /= 0);

     end if;                         -- rising_edge()
 end process u_pulsewidth;

end Behavioral;

On Sat, 08 Nov 2014 09:58:36 +0100, Francesco Messineo wrote:

I'd suggest ALTERA parts , but only because they are the cheapest boards
on *bay , XILINX boards are 2 x the Altera price on *Bay.

An EPM240 CPLD Board $9  (240 cells let you do quite a lot)
http://tinyurl.com/qcusb69

There's also an EPM-570 Board , but the price is almost the same as the
below FPGA , and then the FPGA is the thing to get.

A CycloneII EP2C5T144 FPGA board (With 2 onbard PLL's) $18 - Super value
for the money
http://tinyurl.com/pd326ct

An ALTERA Programmer  $6
http://tinyurl.com/po2qhq2

The only caveat is that they are NOT 5v tolerant , they can do 3v3 or
less.

ALTERA has the free QuartusII WEB Edition , and it works fine under both
Windows & Linux (i'm using Mint17 x64 ... Ubuntu 14.04 based "under the
hood")

I am a VHDL beginner , and completed this (free) course s few month back

Course
http://tinyurl.com/per8lm5

Forum
http://tinyurl.com/pw3b9bv

I have just did a divide by 5 with the EP2C5T144 FPGA board , using one
of the PLL's. I did use so few resources, that it reported 0% of the 4608
Cells utilized, and 1 of 2 PLL's used.

*********** SNIP *************
Fitter Status Successful - Sat Nov  8 23:11:59 2014
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web
Edition
Revision Name div5pll
Top-level Entity Name div5pll
Family Cyclone II
Device EP2C5T144C8
Timing Models Final
Total logic elements 0 / 4,608 ( 0 % )
Total combinational functions 0 / 4,608 ( 0 % )
Dedicated logic registers 0 / 4,608 ( 0 % )
Total registers 0
Total pins 6 / 89 ( 7 % )
Total virtual pins 0
Total memory bits 0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 26 ( 0 % )
Total PLLs 1 / 2 ( 50 % )
*********** SNIP *************

Actually i like Xilinx ISE WebPack better , but the cheap *Bay/Aliexpress
boards are ALTERA Boards , so i have both tools installed on my linux
machine.

If you don't feel like learning VHDL or Verilog , you can do the layout
in "Schematic". ALTERA QuartusII does have an extensive 74xx lib built in
the schematic engine.

See my ansver to assignment 10 , for a QuartusII schematic entry of a 50M
divider. Using use 4 x HC390 dividers in a divide : 100 / 100 / 100 / 50
configuration.
http://tinyurl.com/ntdkcst

Be sure to get these versions of the tools , as both have upgraded their
tools , and the new tools doesn't support the older (cheaper chips).

Altera QuartusII  : Version 13.0sp1  (13.1+ doesn't suport the old CPLD's)
Xilinx ISE   : Version 14.7    (Vivado doesn't support the old stuff)

I suggest to try it out , you can do a lot of logic in a 240 Cell CPLD ,
and MUCH more in the FPGA.

The 4 x HC390 used 16% of the EPM240 logic , and it is less than 1% in
the FPGA. As seen below.

*********** SNIP ***************
Flow Status Successful - Sat Nov  8 23:56:46 2014
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Web
Edition
Revision Name lesson10d
Top-level Entity Name lesson10d
Family Cyclone II
Device EP2C5T144C8
Timing Models Final
Total logic elements 39 / 4,608 ( < 1 % )
Total combinational functions 39 / 4,608 ( < 1 % )
Dedicated logic registers 31 / 4,608 ( < 1 % )
Total registers 31
Total pins 3 / 89 ( 3 % )
Total virtual pins 0
Total memory bits 0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 26 ( 0 % )
Total PLLs 0 / 2 ( 0 % )
*********** SNIP ***************

CFO - Denmark

--
E-mail:xnews5@luna.dyndns.dk

Hi

I’ve done a lot of designs with Altera parts. They are fine parts, but they are not magic. On the CPLD parts, be careful of the speed grade and be sure you do a timing analysis on your design before you buy any hardware. All the design tools are schematic entry capable and free on the web. There’s not a big speed bump when you start using them (like say needing to go learn VHDL…).

Once you get using them, the CPLD's are quite handy for a wide range of projects, way beyond a simple divide by 5. Their bigger cousins (the FPGA’s) aren’t that much more (under $35) and they will do a LOT, especially in the newer series. The Cyclone 2’s had a minimum rated PLL input of 20(?) MHz. The later parts bumped that down to 10 MHz. Much more TimeNuts compatible.

Bob

On Sat, 08 Nov 2014 18:17:09 -0500, Bob Camp wrote:

SNIP

The Cyclone 2’s had a minimum rated PLL

Bob

Hmmm ...

I didn't know the CycloneII had a Min of 20Mhz.
Is that in some doc you can point me to ?

Well it seems to be 11Mhz for the CycloneII ... (Bummer from a T-Nut
perspective)
http://tinyurl.com/opvng2y

I just tried to do a 10 => 100Mhz PLL in the EP2C5T144C8 , using the
"MegaWizzard" , and there were no errors or warnings.

Strange if the Min input is 11Mhz

Anyways , thanx for enlighten me Bob.

CFO

Hi

Back when they were new, I think the limit was higher than that. I suspect the simple answer is “does not work reliably at 10 MHz over all voltages and temperatures”. I haven’t done a Cyclone II design in many years. It’s been almost that long since I looked at a Cy II spec sheet.

Bob