Hi, All, We put a FPGA FFT in dsp_core_rx.v. The output is weird. We have wrote a testbench to make sure that the FFT is right, but after we put it into the entire system, the data received by rx_samples_to_file.cpp are not right. We are trying to simulate the E100, but there are many signals we do not know. Do we have a testbench for E100? We found a testbench single_u2_sim.v under uhd/fpga/usrp2/testbench/, is it for USRP2? As the FAQ suggests, we installed the iverilog_0.10.0. When we try to make, we get some errors about 'Unknown module type'. Is the single_u2_sim.v too old? Do we have a latest testbench? Thanks a lot! Yooxi ../top/USRP2/u2_core.v:337: error: Unknown module type: zpu_wb_top ../top/USRP2/u2_core.v:380: error: Unknown module type: packet_router ../simple_gemac/simple_gemac_wrapper.v:102: error: Unknown module type: ll8_to_fifo19 ../simple_gemac/simple_gemac_wrapper.v:108: error: Unknown module type: fifo19_rxrealign ../simple_gemac/simple_gemac_wrapper.v:113: error: Unknown module type: fifo19_to_fifo36 ../simple_gemac/simple_gemac_wrapper.v:118: error: Unknown module type: fifo_2clock_cascade ../simple_gemac/simple_gemac_wrapper.v:130: error: Unknown module type: fifo_2clock_cascade ../simple_gemac/simple_gemac_wrapper.v:140: error: Unknown module type: fifo36_to_ll8 ../sdr_lib/dsp_core_rx.v:148: error: Unknown module type: sfft ../top/USRP2/u2_core.v:617: error: Unknown module type: vita_rx_chain ../sdr_lib/dsp_core_rx.v:148: error: Unknown module type: sfft ../top/USRP2/u2_core.v:645: error: Unknown module type: vita_rx_chain ../top/USRP2/u2_core.v:666: error: Unknown module type: ext_fifo ../top/USRP2/u2_core.v:694: error: Unknown module type: vita_tx_chain ../serdes/serdes_tx.v:105: error: Unknown module type: fifo_cascade ../serdes/serdes_rx.v:282: error: Unknown module type: fifo_2clock_cascade 17 error(s) during elaboration.

Hi, All, Have found most modules in different folders except ../top/USRP2/u2_core.v:337: error: Unknown module type: zpu_wb_top There is a zpu_wb_top.vhd under opencores/zpu, but it is a .vhd instead of .v How to get around it? How to get through errors like ../models/FIFO_GENERATOR_V6_1.v:1194: sorry: Constant user functions are not yet supported. ../models/FIFO_GENERATOR_V6_1.v:1194: error: Unable to evaluate parameter log2_reads_per_write value: log2_val(<reads_per_write=32'b00000000000000000000000000000000, wid=32>) Thanks, Yooxi 2012/1/3 xi yang <yooxi.yx@gmail.com> > Hi, All, > > We put a FPGA FFT in dsp_core_rx.v. The output is weird. > We have wrote a testbench to make sure that the FFT is right, but after we > put it into the entire system, the data received by rx_samples_to_file.cpp > are not right. > We are trying to simulate the E100, but there are many signals we do not > know. Do we have a testbench for E100? > > We found a testbench single_u2_sim.v under uhd/fpga/usrp2/testbench/, is > it for USRP2? > As the FAQ suggests, we installed the iverilog_0.10.0. > When we try to make, we get some errors about 'Unknown module type'. > Is the single_u2_sim.v too old? Do we have a latest testbench? > > Thanks a lot! > Yooxi > > ../top/USRP2/u2_core.v:337: error: Unknown module type: zpu_wb_top > ../top/USRP2/u2_core.v:380: error: Unknown module type: packet_router > ../simple_gemac/simple_gemac_wrapper.v:102: error: Unknown module type: > ll8_to_fifo19 > ../simple_gemac/simple_gemac_wrapper.v:108: error: Unknown module type: > fifo19_rxrealign > ../simple_gemac/simple_gemac_wrapper.v:113: error: Unknown module type: > fifo19_to_fifo36 > ../simple_gemac/simple_gemac_wrapper.v:118: error: Unknown module type: > fifo_2clock_cascade > ../simple_gemac/simple_gemac_wrapper.v:130: error: Unknown module type: > fifo_2clock_cascade > ../simple_gemac/simple_gemac_wrapper.v:140: error: Unknown module type: > fifo36_to_ll8 > ../sdr_lib/dsp_core_rx.v:148: error: Unknown module type: sfft > ../top/USRP2/u2_core.v:617: error: Unknown module type: vita_rx_chain > ../sdr_lib/dsp_core_rx.v:148: error: Unknown module type: sfft > ../top/USRP2/u2_core.v:645: error: Unknown module type: vita_rx_chain > ../top/USRP2/u2_core.v:666: error: Unknown module type: ext_fifo > ../top/USRP2/u2_core.v:694: error: Unknown module type: vita_tx_chain > ../serdes/serdes_tx.v:105: error: Unknown module type: fifo_cascade > ../serdes/serdes_rx.v:282: error: Unknown module type: fifo_2clock_cascade > 17 error(s) during elaboration. >

When we switched from an aeMB processor to the ZPU we lost the ability to do a fullchip simulation in icarus. ZPU is implemented in VHDL, not verilog, so Icarus can't do it. You should be able to use a commercial simulator. Matt On Tue, Jan 3, 2012 at 1:55 AM, xi yang <yooxi.yx@gmail.com> wrote: > Hi, All, > > Have found most modules in different folders except > ../top/USRP2/u2_core.v:337: error: Unknown module type: zpu_wb_top > There is a zpu_wb_top.vhd under opencores/zpu, but it is a .vhd instead of > .v > How to get around it? > > How to get through errors like > ../models/FIFO_GENERATOR_V6_1.v:1194: sorry: Constant user functions are > not yet supported. > ../models/FIFO_GENERATOR_V6_1.v:1194: error: Unable to evaluate parameter > log2_reads_per_write value: > log2_val(<reads_per_write=32'b00000000000000000000000000000000, wid=32>) > > Thanks, > Yooxi > > 2012/1/3 xi yang <yooxi.yx@gmail.com> > >> Hi, All, >> >> We put a FPGA FFT in dsp_core_rx.v. The output is weird. >> We have wrote a testbench to make sure that the FFT is right, but after >> we put it into the entire system, the data received by >> rx_samples_to_file.cpp are not right. >> We are trying to simulate the E100, but there are many signals we do not >> know. Do we have a testbench for E100? >> >> We found a testbench single_u2_sim.v under uhd/fpga/usrp2/testbench/, is >> it for USRP2? >> As the FAQ suggests, we installed the iverilog_0.10.0. >> When we try to make, we get some errors about 'Unknown module type'. >> Is the single_u2_sim.v too old? Do we have a latest testbench? >> >> Thanks a lot! >> Yooxi >> >> ../top/USRP2/u2_core.v:337: error: Unknown module type: zpu_wb_top >> ../top/USRP2/u2_core.v:380: error: Unknown module type: packet_router >> ../simple_gemac/simple_gemac_wrapper.v:102: error: Unknown module type: >> ll8_to_fifo19 >> ../simple_gemac/simple_gemac_wrapper.v:108: error: Unknown module type: >> fifo19_rxrealign >> ../simple_gemac/simple_gemac_wrapper.v:113: error: Unknown module type: >> fifo19_to_fifo36 >> ../simple_gemac/simple_gemac_wrapper.v:118: error: Unknown module type: >> fifo_2clock_cascade >> ../simple_gemac/simple_gemac_wrapper.v:130: error: Unknown module type: >> fifo_2clock_cascade >> ../simple_gemac/simple_gemac_wrapper.v:140: error: Unknown module type: >> fifo36_to_ll8 >> ../sdr_lib/dsp_core_rx.v:148: error: Unknown module type: sfft >> ../top/USRP2/u2_core.v:617: error: Unknown module type: vita_rx_chain >> ../sdr_lib/dsp_core_rx.v:148: error: Unknown module type: sfft >> ../top/USRP2/u2_core.v:645: error: Unknown module type: vita_rx_chain >> ../top/USRP2/u2_core.v:666: error: Unknown module type: ext_fifo >> ../top/USRP2/u2_core.v:694: error: Unknown module type: vita_tx_chain >> ../serdes/serdes_tx.v:105: error: Unknown module type: fifo_cascade >> ../serdes/serdes_rx.v:282: error: Unknown module type: fifo_2clock_cascade >> 17 error(s) during elaboration. >> > > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >